Re: [PATCH v3 3/3] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-11-05 Thread Bhardwaj, Rajneesh
On 03-Nov-18 12:02 AM, Andy Shevchenko wrote: On Fri, Nov 2, 2018 at 12:37 PM Rajneesh Bhardwaj wrote: The LTR values follow PCIE LTR encoding format and can be decoded as per https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf This adds suppo

Re: [PATCH v3 3/3] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-11-02 Thread Andy Shevchenko
On Fri, Nov 2, 2018 at 12:37 PM Rajneesh Bhardwaj wrote: > > The LTR values follow PCIE LTR encoding format and can be decoded as per > https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf > > This adds support to translate the raw LTR values as read

[PATCH v3 3/3] platform/x86: intel_pmc_core: Decode Snoop / Non Snoop LTR

2018-11-02 Thread Rajneesh Bhardwaj
The LTR values follow PCIE LTR encoding format and can be decoded as per https://pcisig.com/sites/default/files/specification_documents/ECN_LatencyTolnReporting_14Aug08.pdf This adds support to translate the raw LTR values as read from the PMC to meaningful values in nanosecond units of time. Sig