On 1/18/21 1:37 PM, Vincenzo Frascino wrote:
>> If a speculated load is allowed to update this reg, we'd probably need an
>> ISB+DSB (I don't think it does, something to check with the architects).
>>
> I will check this with the architects and let you know.
I spoke to the architects and no spec
On 1/18/21 2:48 PM, Vincenzo Frascino wrote:
>> Are you aware of cases where the TFSR_EL1 value is read other than by an
>> MRS? e.g. are there any cases where checks are elided if TF1 is set? If
>> so, we may need the ISB to order the direct write against subsequent
>> indirect reads.
>>
> Than
Hi Mark,
On 1/18/21 2:14 PM, Mark Rutland wrote:
> On Mon, Jan 18, 2021 at 01:37:35PM +, Vincenzo Frascino wrote:
>> On 1/18/21 12:57 PM, Catalin Marinas wrote:
>
+ if (tfsr_el1 & SYS_TFSR_EL1_TF1) {
+ write_sysreg_s(0, SYS_TFSR_EL1);
+ isb();
>>> While in ge
On Mon, Jan 18, 2021 at 01:37:35PM +, Vincenzo Frascino wrote:
> On 1/18/21 12:57 PM, Catalin Marinas wrote:
> >> + if (tfsr_el1 & SYS_TFSR_EL1_TF1) {
> >> + write_sysreg_s(0, SYS_TFSR_EL1);
> >> + isb();
> > While in general we use ISB after a sysreg update, I haven't convi
On 1/18/21 12:57 PM, Catalin Marinas wrote:
>> +#ifdef CONFIG_KASAN_HW_TAGS
>> +void mte_check_tfsr_el1_no_sync(void)
>> +{
>> +u64 tfsr_el1;
>> +
>> +if (!system_supports_mte())
>> +return;
>> +
>> +tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1);
>> +
>> +/*
>> + * The k
On Fri, Jan 15, 2021 at 12:00:42PM +, Vincenzo Frascino wrote:
> diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h
> index d02aff9f493d..1a715963d909 100644
> --- a/arch/arm64/include/asm/mte.h
> +++ b/arch/arm64/include/asm/mte.h
> @@ -92,5 +92,26 @@ static inline void m
On Fri, Jan 15, 2021 at 12:00:42PM +, Vincenzo Frascino wrote:
> MTE provides a mode that asynchronously updates the TFSR_EL1 register
> when a tag check exception is detected.
>
> To take advantage of this mode the kernel has to verify the status of
> the register at:
> 1. Context switching
MTE provides a mode that asynchronously updates the TFSR_EL1 register
when a tag check exception is detected.
To take advantage of this mode the kernel has to verify the status of
the register at:
1. Context switching
2. Return to user/EL0 (Not required in entry from EL0 since the kernel
did
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