Re: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index 5ca41152cf4b..894e170c503e 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -17,6 +17,14 @@ #define __local_release_fence() \ __asm__

Re: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

haha, I forgot RV32, it needs a #ifdef RV32 srliw #else srli #endif On Thu, Mar 25, 2021 at 7:16 PM kernel test robot wrote: > > Hi, > > Thank you for the patch! Yet something to improve: > > [auto build test ERROR on tip/locking/core] > [also build test ERROR on linux/master

Re: [PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

Hi, Thank you for the patch! Yet something to improve: [auto build test ERROR on tip/locking/core] [also build test ERROR on linux/master linus/master v5.12-rc4 next-20210325] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use

[PATCH v3 4/4] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock

From: Michael Clark Update the RISC-V port to use the generic qspinlock and qrwlock. This patch requires support for xchg for short which are added by a previous patch. Guo fixed up compile error which made by below include sequence: +#include +#include Signed-off-by: Michael Clark