Re: [PATCH v3 6/6] clk: mvebu: Add the peripheral clock driver for Armada 3700

2016-08-15 Thread Stephen Boyd
On 07/19, Gregory CLEMENT wrote: > + > +static const struct clk_ops clk_double_div_ops = { > + .recalc_rate = clk_double_div_recalc_rate, > +}; > + > +static const struct of_device_id armada_3700_periph_clock_of_match[] = { > + { .compatible = "marvell,armada-3700-periph-clock-nb", > +

Re: [PATCH v3 6/6] clk: mvebu: Add the peripheral clock driver for Armada 3700

2016-08-15 Thread Stephen Boyd
On 07/19, Gregory CLEMENT wrote: > + > +static const struct clk_ops clk_double_div_ops = { > + .recalc_rate = clk_double_div_recalc_rate, > +}; > + > +static const struct of_device_id armada_3700_periph_clock_of_match[] = { > + { .compatible = "marvell,armada-3700-periph-clock-nb", > +

[PATCH v3 6/6] clk: mvebu: Add the peripheral clock driver for Armada 3700

2016-07-19 Thread Gregory CLEMENT
These clocks are the ones which will be used as source for the peripherals of the Armada 3700 SoC. On this SoC there is two blocks of clocks: the North bridge one and the South bridge one. Most of them are gatable. Most of the time their rate are their parent rated divided by a ratio depending of

[PATCH v3 6/6] clk: mvebu: Add the peripheral clock driver for Armada 3700

2016-07-19 Thread Gregory CLEMENT
These clocks are the ones which will be used as source for the peripherals of the Armada 3700 SoC. On this SoC there is two blocks of clocks: the North bridge one and the South bridge one. Most of them are gatable. Most of the time their rate are their parent rated divided by a ratio depending of