Hi Rob,
On Tue, 2021-02-23 at 08:31 -0600, Rob Herring wrote:
> On Tue, Feb 23, 2021 at 2:04 AM Benjamin Gaignard
> wrote:
> >
> >
> > Le 23/02/2021 à 01:34, Rob Herring a écrit :
> > > On Mon, Feb 22, 2021 at 01:24:05PM +0100, Benjamin Gaignard wrote:
> > > > The current bindings seem to make
On Tue, Feb 23, 2021 at 2:04 AM Benjamin Gaignard
wrote:
>
>
> Le 23/02/2021 à 01:34, Rob Herring a écrit :
> > On Mon, Feb 22, 2021 at 01:24:05PM +0100, Benjamin Gaignard wrote:
> >> The current bindings seem to make the assumption that the
> >> two VPUs hardware blocks (G1 and G2) are only one
Le 23/02/2021 à 01:34, Rob Herring a écrit :
On Mon, Feb 22, 2021 at 01:24:05PM +0100, Benjamin Gaignard wrote:
The current bindings seem to make the assumption that the
two VPUs hardware blocks (G1 and G2) are only one set of
registers.
After implementing the VPU reset driver and G2 decoder
On Mon, Feb 22, 2021 at 01:24:05PM +0100, Benjamin Gaignard wrote:
> The current bindings seem to make the assumption that the
> two VPUs hardware blocks (G1 and G2) are only one set of
> registers.
> After implementing the VPU reset driver and G2 decoder driver
> it shows that all the VPUs are
The current bindings seem to make the assumption that the
two VPUs hardware blocks (G1 and G2) are only one set of
registers.
After implementing the VPU reset driver and G2 decoder driver
it shows that all the VPUs are independent and don't need to
know about the registers of the other blocks.
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