On Thu, 27 Aug 2020, Mark Brown wrote:
> On Thu, Aug 27, 2020 at 07:56:47AM +0100, Lee Jones wrote:
> > On Wed, 26 Aug 2020, Mark Brown wrote:
>
> > > [2/2] mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC
> > > commit: 53be8bbc2f4058d4a6bfff3dadf34164bcaafa87
>
> > Que?
On Thu, Aug 27, 2020 at 07:56:47AM +0100, Lee Jones wrote:
> On Wed, 26 Aug 2020, Mark Brown wrote:
> > [2/2] mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC
> > commit: 53be8bbc2f4058d4a6bfff3dadf34164bcaafa87
> Que? This is yet to be reviewed.
Sorry, meant to only
On Wed, 26 Aug 2020, Mark Brown wrote:
> On Wed, 19 Aug 2020 15:34:55 +0800, Xu Yilun wrote:
> > This patchset adds the regmap-spi-avmm to support the Intel SPI Slave to
> > AVMM Bus Bridge (spi-avmm) IP block. It also implements the usercase - the
> > driver of Intel Max10 BMC chip which
On Wed, 19 Aug 2020 15:34:55 +0800, Xu Yilun wrote:
> This patchset adds the regmap-spi-avmm to support the Intel SPI Slave to
> AVMM Bus Bridge (spi-avmm) IP block. It also implements the usercase - the
> driver of Intel Max10 BMC chip which integrates this IP block.
>
> Patch #1 implements the
This patchset adds the regmap-spi-avmm to support the Intel SPI Slave to
AVMM Bus Bridge (spi-avmm) IP block. It also implements the usercase - the
driver of Intel Max10 BMC chip which integrates this IP block.
Patch #1 implements the regmap-spi-avmm.
Patch #2 implements the mfd driver of Intel
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