Re: [PATCH v4 0/4] Multiplex sdmmc low jitter clock path

2018-07-10 Thread Peter De Schrijver
Series Acked-By: Peter De Schrijver Peter. On Mon, Jul 09, 2018 at 07:38:54PM +0300, Aapo Vienamo wrote: > The SDMMC clocks have a Low Jitter (LJ) clock path which bypasses a > divider to achieve better jitter performance with high speed signaling > modes. The clock path with the divider is

Re: [PATCH v4 0/4] Multiplex sdmmc low jitter clock path

2018-07-10 Thread Peter De Schrijver
Series Acked-By: Peter De Schrijver Peter. On Mon, Jul 09, 2018 at 07:38:54PM +0300, Aapo Vienamo wrote: > The SDMMC clocks have a Low Jitter (LJ) clock path which bypasses a > divider to achieve better jitter performance with high speed signaling > modes. The clock path with the divider is

[PATCH v4 0/4] Multiplex sdmmc low jitter clock path

2018-07-09 Thread Aapo Vienamo
The SDMMC clocks have a Low Jitter (LJ) clock path which bypasses a divider to achieve better jitter performance with high speed signaling modes. The clock path with the divider is needed by some of the slower signaling modes. This series automatically multiplexes the LJ and non-LJ clock paths

[PATCH v4 0/4] Multiplex sdmmc low jitter clock path

2018-07-09 Thread Aapo Vienamo
The SDMMC clocks have a Low Jitter (LJ) clock path which bypasses a divider to achieve better jitter performance with high speed signaling modes. The clock path with the divider is needed by some of the slower signaling modes. This series automatically multiplexes the LJ and non-LJ clock paths