Re: [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup

2020-05-22 Thread Kishon Vijay Abraham I
Hi Rob, On 5/22/2020 10:15 PM, Rob Herring wrote: > On Thu, May 21, 2020 at 5:35 AM Kishon Vijay Abraham I wrote: >> >> Hi Rob, >> >> On 5/21/2020 3:04 AM, Rob Herring wrote: >>> On Wed, May 06, 2020 at 08:44:22PM +0530, Kishon Vijay Abraham I wrote: Cadence driver uses "mem" memory resource

Re: [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup

2020-05-22 Thread Rob Herring
On Thu, May 21, 2020 at 5:35 AM Kishon Vijay Abraham I wrote: > > Hi Rob, > > On 5/21/2020 3:04 AM, Rob Herring wrote: > > On Wed, May 06, 2020 at 08:44:22PM +0530, Kishon Vijay Abraham I wrote: > >> Cadence driver uses "mem" memory resource to obtain the offset of > >> configuration space address

Re: [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup

2020-05-21 Thread Kishon Vijay Abraham I
Hi Rob, On 5/21/2020 3:04 AM, Rob Herring wrote: > On Wed, May 06, 2020 at 08:44:22PM +0530, Kishon Vijay Abraham I wrote: >> Cadence driver uses "mem" memory resource to obtain the offset of >> configuration space address region, memory space address region and >> message space address region. Th

Re: [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup

2020-05-20 Thread Rob Herring
On Wed, May 06, 2020 at 08:44:22PM +0530, Kishon Vijay Abraham I wrote: > Cadence driver uses "mem" memory resource to obtain the offset of > configuration space address region, memory space address region and > message space address region. The obtained offset is used to program > the Address Tran

[PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup

2020-05-06 Thread Kishon Vijay Abraham I
Cadence driver uses "mem" memory resource to obtain the offset of configuration space address region, memory space address region and message space address region. The obtained offset is used to program the Address Translation Unit (ATU). However certain platforms like TI's J721E SoC require the ab