Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-23 Thread Anurup M
On Tuesday 21 February 2017 05:39 PM, Will Deacon wrote: On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote: On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: The L3 cache PMU use N-N SPI interrupt which has no support in kernel mainline. Could you elaborate on what you

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-23 Thread Anurup M
On Tuesday 21 February 2017 05:39 PM, Will Deacon wrote: On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote: On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: The L3 cache PMU use N-N SPI interrupt which has no support in kernel mainline. Could you elaborate on what you

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-21 Thread Will Deacon
On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote: > On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: > > The L3 cache PMU use N-N SPI interrupt which has no support > > in kernel mainline. > > Could you elaborate on what you mean by this? > > I don't understand what is meant

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-21 Thread Will Deacon
On Mon, Feb 20, 2017 at 11:09:43AM +, Mark Rutland wrote: > On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: > > The L3 cache PMU use N-N SPI interrupt which has no support > > in kernel mainline. > > Could you elaborate on what you mean by this? > > I don't understand what is meant

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-21 Thread Marc Zyngier
On 21/02/17 07:07, Anurup M wrote: > Adding Marc. > > On Monday 20 February 2017 04:39 PM, Mark Rutland wrote: >> On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: >>> The L3 cache PMU use N-N SPI interrupt which has no support >>> in kernel mainline. >> Could you elaborate on what you

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-21 Thread Marc Zyngier
On 21/02/17 07:07, Anurup M wrote: > Adding Marc. > > On Monday 20 February 2017 04:39 PM, Mark Rutland wrote: >> On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: >>> The L3 cache PMU use N-N SPI interrupt which has no support >>> in kernel mainline. >> Could you elaborate on what you

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-20 Thread Anurup M
Adding Marc. On Monday 20 February 2017 04:39 PM, Mark Rutland wrote: On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: The L3 cache PMU use N-N SPI interrupt which has no support in kernel mainline. Could you elaborate on what you mean by this? I don't understand what is meant here.

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-20 Thread Anurup M
Adding Marc. On Monday 20 February 2017 04:39 PM, Mark Rutland wrote: On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: The L3 cache PMU use N-N SPI interrupt which has no support in kernel mainline. Could you elaborate on what you mean by this? I don't understand what is meant here.

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-20 Thread Mark Rutland
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: > The L3 cache PMU use N-N SPI interrupt which has no support > in kernel mainline. Could you elaborate on what you mean by this? I don't understand what is meant here. How exactly are the interrupts wired up in HW, and what exactly is

Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-20 Thread Mark Rutland
On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote: > The L3 cache PMU use N-N SPI interrupt which has no support > in kernel mainline. Could you elaborate on what you mean by this? I don't understand what is meant here. How exactly are the interrupts wired up in HW, and what exactly is

[PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-19 Thread Anurup M
The L3 cache PMU use N-N SPI interrupt which has no support in kernel mainline. So use hrtimer to poll and update event counter to avoid overflow condition for L3 cache PMU. A interval of 10 seconds is used for the hrtimer. The time interval can be configured in the sysfs. Signed-off-by: Dikshit

[PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow

2017-02-19 Thread Anurup M
The L3 cache PMU use N-N SPI interrupt which has no support in kernel mainline. So use hrtimer to poll and update event counter to avoid overflow condition for L3 cache PMU. A interval of 10 seconds is used for the hrtimer. The time interval can be configured in the sysfs. Signed-off-by: Dikshit