Re: [PATCH v4 1/2] perf/smmuv3: Don't reserve the PMCG register spaces

2021-02-01 Thread Leizhen (ThunderTown)
On 2021/2/1 20:54, Will Deacon wrote: > On Sat, Jan 30, 2021 at 03:14:13PM +0800, Zhen Lei wrote: >> According to the SMMUv3 specification: >> Each PMCG counter group is represented by one 4KB page (Page 0) with one >> optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION

Re: [PATCH v4 1/2] perf/smmuv3: Don't reserve the PMCG register spaces

2021-02-01 Thread Will Deacon
On Sat, Jan 30, 2021 at 03:14:13PM +0800, Zhen Lei wrote: > According to the SMMUv3 specification: > Each PMCG counter group is represented by one 4KB page (Page 0) with one > optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION > DEFINED base addresses. > > This means that

Re: [PATCH v4 1/2] perf/smmuv3: Don't reserve the PMCG register spaces

2021-02-01 Thread Robin Murphy
On 2021-01-30 07:14, Zhen Lei wrote: According to the SMMUv3 specification: Each PMCG counter group is represented by one 4KB page (Page 0) with one optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION DEFINED base addresses. This means that the PMCG register spaces may be

Re: [PATCH v4 1/2] perf/smmuv3: Don't reserve the PMCG register spaces

2021-01-30 Thread Leizhen (ThunderTown)
Hi, Robin: Can you review this patch again? On 2021/1/30 15:14, Zhen Lei wrote: > According to the SMMUv3 specification: > Each PMCG counter group is represented by one 4KB page (Page 0) with one > optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION > DEFINED base

[PATCH v4 1/2] perf/smmuv3: Don't reserve the PMCG register spaces

2021-01-30 Thread Zhen Lei
According to the SMMUv3 specification: Each PMCG counter group is represented by one 4KB page (Page 0) with one optional additional 4KB page (Page 1), both of which are at IMPLEMENTATION DEFINED base addresses. This means that the PMCG register spaces may be within the 64KB pages of the SMMUv3