On Monday 20 April 2015 11:49:37 Feng Kan wrote:
> >
> > Obviously they appear on the PCI host bridge in order, because that
> > is a how PCI works. My question was about what happens then. On a lot
> > of SoCs, there is something like an AXI bus that uses posted
> > transactions between PCI and
On Monday 20 April 2015 11:49:37 Feng Kan wrote:
Obviously they appear on the PCI host bridge in order, because that
is a how PCI works. My question was about what happens then. On a lot
of SoCs, there is something like an AXI bus that uses posted
transactions between PCI and RAM, so you
On Sun, Apr 19, 2015 at 12:55 PM, Arnd Bergmann wrote:
> On Sunday 19 April 2015 11:40:09 Duc Dang wrote:
>> On Fri, Apr 17, 2015 at 7:10 AM, Arnd Bergmann wrote:
>> > On Friday 17 April 2015 02:50:07 Duc Dang wrote:
>> >> +
>> >> + /*
>> >> +* MSIINTn (n is 0..F) indicates if
On Sun, Apr 19, 2015 at 12:55 PM, Arnd Bergmann a...@arndb.de wrote:
On Sunday 19 April 2015 11:40:09 Duc Dang wrote:
On Fri, Apr 17, 2015 at 7:10 AM, Arnd Bergmann a...@arndb.de wrote:
On Friday 17 April 2015 02:50:07 Duc Dang wrote:
+
+ /*
+* MSIINTn (n is 0..F) indicates
On Sunday 19 April 2015 11:40:09 Duc Dang wrote:
> On Fri, Apr 17, 2015 at 7:10 AM, Arnd Bergmann wrote:
> > On Friday 17 April 2015 02:50:07 Duc Dang wrote:
> >> +
> >> + /*
> >> +* MSIINTn (n is 0..F) indicates if there is a pending MSI
> >> interrupt
> >> +* If bit x of
On Fri, Apr 17, 2015 at 7:10 AM, Arnd Bergmann wrote:
> On Friday 17 April 2015 02:50:07 Duc Dang wrote:
>> +
>> + /*
>> +* MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt
>> +* If bit x of this register is set (x is 0..7), one or more
>> interupts
>> +
On Sunday 19 April 2015 11:40:09 Duc Dang wrote:
On Fri, Apr 17, 2015 at 7:10 AM, Arnd Bergmann a...@arndb.de wrote:
On Friday 17 April 2015 02:50:07 Duc Dang wrote:
+
+ /*
+* MSIINTn (n is 0..F) indicates if there is a pending MSI
interrupt
+* If bit x of this
On Fri, Apr 17, 2015 at 7:10 AM, Arnd Bergmann a...@arndb.de wrote:
On Friday 17 April 2015 02:50:07 Duc Dang wrote:
+
+ /*
+* MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt
+* If bit x of this register is set (x is 0..7), one or more
interupts
+
On Friday 17 April 2015 02:50:07 Duc Dang wrote:
> +
> + /*
> +* MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt
> +* If bit x of this register is set (x is 0..7), one or more interupts
> +* corresponding to MSInIRx is set.
> +*/
> +
On Friday 17 April 2015 02:50:07 Duc Dang wrote:
+
+ /*
+* MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt
+* If bit x of this register is set (x is 0..7), one or more interupts
+* corresponding to MSInIRx is set.
+*/
+
X-Gene v1 SoC supports total 2048 MSI/MSIX vectors coalesced into
16 HW IRQ lines.
Signed-off-by: Duc Dang
Signed-off-by: Tanmay Inamdar
---
drivers/pci/host/Kconfig | 6 +
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pci-xgene-msi.c | 410
X-Gene v1 SoC supports total 2048 MSI/MSIX vectors coalesced into
16 HW IRQ lines.
Signed-off-by: Duc Dang dhd...@apm.com
Signed-off-by: Tanmay Inamdar tinam...@apm.com
---
drivers/pci/host/Kconfig | 6 +
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pci-xgene-msi.c | 410
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