Re: [PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

2016-12-13 Thread Gautham R Shenoy
Hi Balbir, On Tue, Dec 13, 2016 at 09:13:26PM +1100, Balbir Singh wrote: > > > On 10/12/16 00:32, Gautham R. Shenoy wrote: > > From: "Gautham R. Shenoy" > > diff --git a/arch/powerpc/include/asm/cpuidle.h > > b/arch/powerpc/include/asm/cpuidle.h > > index

Re: [PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

2016-12-13 Thread Gautham R Shenoy
Hi Balbir, On Tue, Dec 13, 2016 at 09:13:26PM +1100, Balbir Singh wrote: > > > On 10/12/16 00:32, Gautham R. Shenoy wrote: > > From: "Gautham R. Shenoy" > > diff --git a/arch/powerpc/include/asm/cpuidle.h > > b/arch/powerpc/include/asm/cpuidle.h > > index 3919332..0a3255b 100644 > > ---

Re: [PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

2016-12-13 Thread Balbir Singh
On 10/12/16 00:32, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > Currently all the low-power idle states are expected to wake up > at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ > that puts the CPU to an idle state and never returns. > >

Re: [PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

2016-12-13 Thread Balbir Singh
On 10/12/16 00:32, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > Currently all the low-power idle states are expected to wake up > at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ > that puts the CPU to an idle state and never returns. > > On ISA_300, when the ESL

[PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

2016-12-09 Thread Gautham R. Shenoy
From: "Gautham R. Shenoy" Currently all the low-power idle states are expected to wake up at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ that puts the CPU to an idle state and never returns. On ISA_300, when the ESL and EC bits in the PSSCR are zero,

[PATCH v4 1/4] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

2016-12-09 Thread Gautham R. Shenoy
From: "Gautham R. Shenoy" Currently all the low-power idle states are expected to wake up at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ that puts the CPU to an idle state and never returns. On ISA_300, when the ESL and EC bits in the PSSCR are zero, the CPU is expected to