On Wed, Mar 12, 2014 at 12:02 AM, Srikanth Thokala wrote:
> On Tue, Mar 11, 2014 at 7:14 PM, Jassi Brar
> wrote:
>> On 11 March 2014 00:00, Srikanth Thokala wrote:
>>> On Mon, Mar 10, 2014 at 9:30 PM, Jassi Brar
>>> wrote:
On Thu, Mar 6, 2014 at 7:18 PM, Srikanth Thokala
wrote:
>>
On Tue, Mar 11, 2014 at 7:14 PM, Jassi Brar wrote:
> On 11 March 2014 00:00, Srikanth Thokala wrote:
>> On Mon, Mar 10, 2014 at 9:30 PM, Jassi Brar wrote:
>>> On Thu, Mar 6, 2014 at 7:18 PM, Srikanth Thokala wrote:
>>>
+static struct dma_async_tx_descriptor *
+xilinx_vdma_dma_prep_int
On 11 March 2014 00:00, Srikanth Thokala wrote:
> On Mon, Mar 10, 2014 at 9:30 PM, Jassi Brar wrote:
>> On Thu, Mar 6, 2014 at 7:18 PM, Srikanth Thokala wrote:
>>
>>> +static struct dma_async_tx_descriptor *
>>> +xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
>>> +
On Mon, Mar 10, 2014 at 9:30 PM, Jassi Brar wrote:
> On Thu, Mar 6, 2014 at 7:18 PM, Srikanth Thokala wrote:
>
>> +static struct dma_async_tx_descriptor *
>> +xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
>> +struct dma_interleaved_template *xt,
>> +
On Thu, Mar 6, 2014 at 7:18 PM, Srikanth Thokala wrote:
> +static struct dma_async_tx_descriptor *
> +xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
> +struct dma_interleaved_template *xt,
> +unsigned long flags)
> +{
> +
This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type video target peripherals. The core provides efficient two
dimensional DMA operations with independent asyn
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