Hi Boris,
On 5/5/2020 3:00 pm, Boris Brezillon wrote:
Hello Vadivel,
On Tue, 5 May 2020 13:28:58 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
ebu_nand: ebu_nand@e0f0 {
compatible = "intel,lgm-ebu-nand";
reg = <0xe0f0 0x100
Hello Vadivel,
On Tue, 5 May 2020 13:28:58 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> >>
> >> ebu_nand: ebu_nand@e0f0 {
> >> compatible = "intel,lgm-ebu-nand";
> >> reg = <0xe0f0 0x100
> >>
Hi Boris,
On 4/5/2020 4:58 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 16:50:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 4/5/2020 3:17 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 15:15:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very
Hi Boris,
On 4/5/2020 4:58 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 16:50:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 4/5/2020 3:17 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 15:15:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very
On Mon, 4 May 2020 16:50:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> Hi Boris,
>
> On 4/5/2020 3:17 pm, Boris Brezillon wrote:
> > On Mon, 4 May 2020 15:15:08 +0800
> > "Ramuthevar, Vadivel MuruganX"
> > wrote:
> >
> >> Hi Boris,
> >>
> >> Thank you very much for the prompt review
Hi Boris,
On 4/5/2020 3:17 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 15:15:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very much for the prompt review and suggestions...
On 4/5/2020 3:08 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 10:02:35 +0800
On Mon, 4 May 2020 15:15:08 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> Hi Boris,
>
>Thank you very much for the prompt review and suggestions...
>
> On 4/5/2020 3:08 pm, Boris Brezillon wrote:
> > On Mon, 4 May 2020 10:02:35 +0800
> > "Ramuthevar, Vadivel MuruganX"
> > wrote:
> >
>
Hi Boris,
Thank you very much for the prompt review and suggestions...
On 4/5/2020 3:08 pm, Boris Brezillon wrote:
On Mon, 4 May 2020 10:02:35 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 30/4/2020 9:01 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 14:36:00 +0200
Boris
On Mon, 4 May 2020 10:02:35 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> Hi Boris,
>
> On 30/4/2020 9:01 pm, Boris Brezillon wrote:
> > On Thu, 30 Apr 2020 14:36:00 +0200
> > Boris Brezillon wrote:
> >
> >> On Thu, 30 Apr 2020 17:07:03 +0800
> >> "Ramuthevar, Vadivel MuruganX"
> >> wrote:
Hi Boris,
On 30/4/2020 9:01 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 14:36:00 +0200
Boris Brezillon wrote:
On Thu, 30 Apr 2020 17:07:03 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
The question is, is it the same value we have in nand_pa or it is
different?
Different
Hi Boris,
Thank you very much for the review comments and your time...
On 30/4/2020 9:01 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 14:36:00 +0200
Boris Brezillon wrote:
On Thu, 30 Apr 2020 17:07:03 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
The question is, is it the same value
Hi Boris,
Thank you very much for the review comments and giving inputs...
On 30/4/2020 8:36 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 17:07:03 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
The question is, is it the same value we have in nand_pa or it is
different?
Different
On Thu, 30 Apr 2020 14:36:00 +0200
Boris Brezillon wrote:
> On Thu, 30 Apr 2020 17:07:03 +0800
> "Ramuthevar, Vadivel MuruganX"
> wrote:
>
> > >>> The question is, is it the same value we have in nand_pa or it is
> > >>> different?
> > >>>
> > >> Different address which is 0xE140
On Thu, 30 Apr 2020 17:07:03 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> >>> The question is, is it the same value we have in nand_pa or it is
> >>> different?
> >>>
> >> Different address which is 0xE140 NAND_BASE_PHY address.
> >
> > Then why didn't you tell me they didn't match
Hi Boris,
On 30/4/2020 4:36 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 16:30:15 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
And now I'd like you to explain why 5 is the right value for that field
(I guess that has to do with the position of the CS/ALE/CLE pins).
5 : bit 26, 25, 24,
On Thu, 30 Apr 2020 16:30:15 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> >>>
> >>> And now I'd like you to explain why 5 is the right value for that field
> >>> (I guess that has to do with the position of the CS/ALE/CLE pins).
> >>
> >> 5 : bit 26, 25, 24, 23, 22 to be included for
H Boris,
On 30/4/2020 4:21 pm, Boris Brezillon wrote:
On Thu, 30 Apr 2020 15:50:30 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very much for keep reviewing the patches and more queries...
On 29/4/2020 11:31 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 23:18:31
On Thu, 30 Apr 2020 15:50:30 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> Hi Boris,
>
>Thank you very much for keep reviewing the patches and more queries...
>
> On 29/4/2020 11:31 pm, Boris Brezillon wrote:
> > On Wed, 29 Apr 2020 23:18:31 +0800
> > "Ramuthevar, Vadivel MuruganX"
> >
Hi Boris,
Thank you very much for keep reviewing the patches and more queries...
On 29/4/2020 11:31 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 23:18:31 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 29/4/2020 10:48 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 22:33:37
On Wed, 29 Apr 2020 23:18:31 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> Hi Boris,
>
> On 29/4/2020 10:48 pm, Boris Brezillon wrote:
> > On Wed, 29 Apr 2020 22:33:37 +0800
> > "Ramuthevar, Vadivel MuruganX"
> > wrote:
> >
> >> Hi Boris,
> >>
> >> On 29/4/2020 10:22 pm, Boris Brezillon
Hi Boris,
On 29/4/2020 11:18 pm, Ramuthevar, Vadivel MuruganX wrote:
+ writel(lower_32_bits(ebu_host->cs[ebu_host->cs_num].nand_pa) |
+ EBU_ADDR_SEL_REGEN | EBU_ADDR_MASK,
+ ebu_host->ebu + EBU_ADDR_SEL(reg));
+
+ writel(EBU_MEM_BASE_CS_0 | EBU_ADDR_MASK |
Hi Boris,
On 29/4/2020 10:48 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 22:33:37 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
On 29/4/2020 10:22 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
+
+#define EBU_ADDR_SEL(n)
On Wed, 29 Apr 2020 22:33:37 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> Hi Boris,
>
> On 29/4/2020 10:22 pm, Boris Brezillon wrote:
> > On Wed, 29 Apr 2020 18:42:05 +0800
> > "Ramuthevar, Vadivel MuruganX"
> > wrote:
> >
> >> +
> >> +#define EBU_ADDR_SEL(n) (0x20 + (n) * 4)
>
Hi Boris,
On 29/4/2020 10:22 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
+
+#define EBU_ADDR_SEL(n)(0x20 + (n) * 4)
+#define EBU_ADDR_MASK (5 << 4)
It's still unclear what ADDR_MASK is for. Can you add a
Hi Boris,
Thank you very much for the review comments and your time...
On 29/4/2020 9:32 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 21:29:40 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
Hi Boris,
Thank you very much for the review comments and your time..
On 29/4/2020 7:33 pm,
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> +
> +#define EBU_ADDR_SEL(n) (0x20 + (n) * 4)
> +#define EBU_ADDR_MASK(5 << 4)
It's still unclear what ADDR_MASK is for. Can you add a comment
explaining what it does?
> +#define
On Wed, 29 Apr 2020 21:29:40 +0800
"Ramuthevar, Vadivel MuruganX"
wrote:
> Hi Boris,
>
> Thank you very much for the review comments and your time..
>
> On 29/4/2020 7:33 pm, Boris Brezillon wrote:
> > On Wed, 29 Apr 2020 18:42:05 +0800
> > "Ramuthevar,Vadivel MuruganX"
> > wrote:
> >
Hi Boris,
Thank you very much for the review comments and your time..
On 29/4/2020 7:33 pm, Boris Brezillon wrote:
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar,Vadivel MuruganX"
wrote:
+#define NAND_WRITE_CMD (EBU_CON_CS_P_LOW | HSNAND_CLE_OFFS)
+#define NAND_WRITE_ADDR
On Wed, 29 Apr 2020 18:42:05 +0800
"Ramuthevar,Vadivel MuruganX"
wrote:
> +#define NAND_WRITE_CMD (EBU_CON_CS_P_LOW | HSNAND_CLE_OFFS)
> +#define NAND_WRITE_ADDR (EBU_CON_CS_P_LOW | HSNAND_ALE_OFFS)
> +
I thought we agreed on dropping those definitions.
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
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