Re: [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210

2015-01-19 Thread MyungJoo Ham
> > This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has > one memory bus to translate data between DRAM and eMMC/sub-IPs because > Exynos4210 must need only one regulator for memory bus. > > Following list specifies the detailed relation between memory bus clock and >

Re: [PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210

2015-01-19 Thread MyungJoo Ham
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has one memory bus to translate data between DRAM and eMMC/sub-IPs because Exynos4210 must need only one regulator for memory bus. Following list specifies the detailed relation between memory bus clock and sub-IPs:

[PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210

2015-01-14 Thread Chanwoo Choi
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has one memory bus to translate data between DRAM and eMMC/sub-IPs because Exynos4210 must need only one regulator for memory bus. Following list specifies the detailed relation between memory bus clock and sub-IPs: - DMC/ACP

[PATCH v4 6/9] ARM: dts: Add memory bus node for Exynos4210

2015-01-14 Thread Chanwoo Choi
This patch adds the memory bus node for Exynos4210 SoC. Exynos4210 SoC has one memory bus to translate data between DRAM and eMMC/sub-IPs because Exynos4210 must need only one regulator for memory bus. Following list specifies the detailed relation between memory bus clock and sub-IPs: - DMC/ACP