On Mon, Mar 23, 2015 at 04:24:26PM +, Appana Durga Kedareswara Rao wrote:
> > > +static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan,
> > > + dma_cookie_t cookie,
> > > + struct dma_tx_state *txstate) {
>
Soren Brinkmann;
> dmaeng...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Appana Durga Kedareswara Rao; Anirudha Sarangi;
> Srikanth Vemula; Srikanth Thokala
> Subject: Re: [PATCH v5] dma: Add Xilinx AXI Direct Memory Access Engine
> driver support
On Mon, Mar 02, 2015 at 11:25:11PM +0530, Kedareswara rao Appana wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwidth direct memory access between memory and AXI4-Stream
> type target peripherals.
>
> Signed-o
al Simek; Soren
> Brinkmann; Srikanth Vemula; linux-kernel@vger.kernel.org; Srikanth
> Thokala; Anirudha Sarangi; dmaeng...@vger.kernel.org; Appana Durga
> Kedareswara Rao; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v5] dma: Add Xilinx AXI Direct Memory Access Engine
> driv
Brinkmann; dmaeng...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Appana Durga
> Kedareswara Rao; Anirudha Sarangi; Srikanth Vemula; Srikanth Thokala
> Subject: Re: [PATCH v5] dma: Add Xilinx AXI Direct Memory Access Engine
> driver support
>
&g
rinkmann; Srikanth Vemula; linux-kernel@vger.kernel.org; Srikanth
> Thokala; Anirudha Sarangi; dmaeng...@vger.kernel.org; Appana Durga
> Kedareswara Rao; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v5] dma: Add Xilinx AXI Direct Memory Access Engine
> driver support
>
&
On Mon, 2015-03-02 at 23:25 +0530, Kedareswara rao Appana wrote:
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -425,6 +425,19 @@ config IMG_MDC_DMA
> help
> Enable support for the IMG multi-threaded DMA controller (MDC).
>
> +config XILINX_DMA
> + tristate "Xilinx
Hello,
Here are my comments:
You are not making efficient use of DMA's coalesce capability and
chaining because you could keep a list of pending descriptors, chain
and process them with a single IRQ by setting the coalese field equal
to the number of End Of Frame bits set in the entire list. This
Hello!
I looked through your driver and have some comments.
On Mon, Mar 02, 2015 at 11:25:11PM +0530, Kedareswara rao Appana wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwidth direct memory access between m
This is the driver for the AXI Direct Memory Access (AXI DMA)
core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type target peripherals.
Signed-off-by: Srikanth Thokala
Signed-off-by: Kedareswara rao Appana
---
This patch is re
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