On Tue, Dec 19, 2017 at 12:45:30PM +, Gustavo Pimentel wrote:
> Tested-By: Gustavo Pimentel
>
> Using an arc board with USB and SATA end points with a root complex PCIe IP
> core
> version 5.00, I ran the the following tests:
> - I checked that all end points
On Tue, Dec 19, 2017 at 12:45:30PM +, Gustavo Pimentel wrote:
> Tested-By: Gustavo Pimentel
>
> Using an arc board with USB and SATA end points with a root complex PCIe IP
> core
> version 5.00, I ran the the following tests:
> - I checked that all end points were listed correctly;
> - I
On Tue, Dec 19, 2017 at 10:19:18AM +, Lorenzo Pieralisi wrote:
> On Mon, Nov 20, 2017 at 02:32:04PM +0100, Niklas Cassel wrote:
> > Use the DMA-API to get the MSI address. This address will be written to
> > our PCI config space and to the register which determines which AXI
> > address the
On Tue, Dec 19, 2017 at 10:19:18AM +, Lorenzo Pieralisi wrote:
> On Mon, Nov 20, 2017 at 02:32:04PM +0100, Niklas Cassel wrote:
> > Use the DMA-API to get the MSI address. This address will be written to
> > our PCI config space and to the register which determines which AXI
> > address the
On Tue, Dec 19, 2017 at 12:45:30PM +, Gustavo Pimentel wrote:
>Tested-By: Gustavo Pimentel
>Using an arc board with USB and SATA end points with a root complex PCIe
>IP core version 5.00, I ran the the following tests:
> - I checked that all end
On Tue, Dec 19, 2017 at 12:45:30PM +, Gustavo Pimentel wrote:
>Tested-By: Gustavo Pimentel
>Using an arc board with USB and SATA end points with a root complex PCIe
>IP core version 5.00, I ran the the following tests:
> - I checked that all end points were listed correctly;
>
On Mon, Nov 20, 2017 at 02:32:04PM +0100, Niklas Cassel wrote:
> Use the DMA-API to get the MSI address. This address will be written to
> our PCI config space and to the register which determines which AXI
> address the DWC IP will spoof for incoming MSI irqs.
>
> Since it is a PCIe endpoint
On Mon, Nov 20, 2017 at 02:32:04PM +0100, Niklas Cassel wrote:
> Use the DMA-API to get the MSI address. This address will be written to
> our PCI config space and to the register which determines which AXI
> address the DWC IP will spoof for incoming MSI irqs.
>
> Since it is a PCIe endpoint
Hi Gustavo,
On Thu, Dec 14, 2017 at 12:38:04PM +, Gustavo Pimentel wrote:
> Ok. I will compile and test it now.
Have you managed to retrieve the patches and test them ?
Thank you,
Lorenzo
> Thanks.
>
>
> On 14/12/2017 12:22, Lorenzo Pieralisi wrote:
> > On Thu, Dec 14, 2017 at 12:16:38PM
Hi Gustavo,
On Thu, Dec 14, 2017 at 12:38:04PM +, Gustavo Pimentel wrote:
> Ok. I will compile and test it now.
Have you managed to retrieve the patches and test them ?
Thank you,
Lorenzo
> Thanks.
>
>
> On 14/12/2017 12:22, Lorenzo Pieralisi wrote:
> > On Thu, Dec 14, 2017 at 12:16:38PM
Hi Lorenzo,
Yes, I have retrieve patches and performed some basic tests without having any
problems till now.
However, I'm still trying to test the changes with our automated system. It's
being very difficult to find a time slot available for running this tests.
I hope in this week I could give
Hi Lorenzo,
Yes, I have retrieve patches and performed some basic tests without having any
problems till now.
However, I'm still trying to test the changes with our automated system. It's
being very difficult to find a time slot available for running this tests.
I hope in this week I could give
Ok. I will compile and test it now.
Thanks.
On 14/12/2017 12:22, Lorenzo Pieralisi wrote:
> On Thu, Dec 14, 2017 at 12:16:38PM +, Gustavo Pimentel wrote:
>> Hi Niklas and Lorenzo,
>>
>> I'm going to work on PCI software development now as told by Joao and I will
>> test your code now.
>>
>>
Ok. I will compile and test it now.
Thanks.
On 14/12/2017 12:22, Lorenzo Pieralisi wrote:
> On Thu, Dec 14, 2017 at 12:16:38PM +, Gustavo Pimentel wrote:
>> Hi Niklas and Lorenzo,
>>
>> I'm going to work on PCI software development now as told by Joao and I will
>> test your code now.
>>
>>
On Thu, Dec 14, 2017 at 12:16:38PM +, Gustavo Pimentel wrote:
> Hi Niklas and Lorenzo,
>
> I'm going to work on PCI software development now as told by Joao and I will
> test your code now.
>
> I was retrieving the patches through the patchwork
>
On Thu, Dec 14, 2017 at 12:16:38PM +, Gustavo Pimentel wrote:
> Hi Niklas and Lorenzo,
>
> I'm going to work on PCI software development now as told by Joao and I will
> test your code now.
>
> I was retrieving the patches through the patchwork
>
Hi Niklas and Lorenzo,
I'm going to work on PCI software development now as told by João and I will
test your code now.
I was retrieving the patches through the patchwork
https://patchwork.ozlabs.org/project/linux-pci/list/?submitter=65580 and I
notice that its missing the patch 13 and 17, is
Hi Niklas and Lorenzo,
I'm going to work on PCI software development now as told by João and I will
test your code now.
I was retrieving the patches through the patchwork
https://patchwork.ozlabs.org/project/linux-pci/list/?submitter=65580 and I
notice that its missing the patch 13 and 17, is
Hi Niklas,
Às 1:59 PM de 12/13/2017, Niklas Cassel escreveu:
> On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote:
>> Jingoo, Joao,
>>
>> I am expecting your testing on the series and ACKs on the dwc related
>> patches please, according to v4 review - I will mark them as needs
>>
Hi Niklas,
Às 1:59 PM de 12/13/2017, Niklas Cassel escreveu:
> On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote:
>> Jingoo, Joao,
>>
>> I am expecting your testing on the series and ACKs on the dwc related
>> patches please, according to v4 review - I will mark them as needs
>>
Jingoo, Joao,
Niklas has a point. I can't apply this series without your testing
and review, so please do test/ack if you deem that suitable.
On Wed, Dec 13, 2017 at 02:59:54PM +0100, Niklas Cassel wrote:
> On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote:
> > Jingoo, Joao,
> >
Jingoo, Joao,
Niklas has a point. I can't apply this series without your testing
and review, so please do test/ack if you deem that suitable.
On Wed, Dec 13, 2017 at 02:59:54PM +0100, Niklas Cassel wrote:
> On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote:
> > Jingoo, Joao,
> >
On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote:
> Jingoo, Joao,
>
> I am expecting your testing on the series and ACKs on the dwc related
> patches please, according to v4 review - I will mark them as needs
> review/ACK waiting for you to chime in.
>
> v4 thread:
>
>
On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote:
> Jingoo, Joao,
>
> I am expecting your testing on the series and ACKs on the dwc related
> patches please, according to v4 review - I will mark them as needs
> review/ACK waiting for you to chime in.
>
> v4 thread:
>
>
Jingoo, Joao,
I am expecting your testing on the series and ACKs on the dwc related
patches please, according to v4 review - I will mark them as needs
review/ACK waiting for you to chime in.
v4 thread:
https://patchwork.ozlabs.org/patch/833882/
Thanks,
Lorenzo
On Mon, Nov 20, 2017 at
Jingoo, Joao,
I am expecting your testing on the series and ACKs on the dwc related
patches please, according to v4 review - I will mark them as needs
review/ACK waiting for you to chime in.
v4 thread:
https://patchwork.ozlabs.org/patch/833882/
Thanks,
Lorenzo
On Mon, Nov 20, 2017 at
Use the DMA-API to get the MSI address. This address will be written to
our PCI config space and to the register which determines which AXI
address the DWC IP will spoof for incoming MSI irqs.
Since it is a PCIe endpoint device, rather than the CPU, that is supposed
to write to the MSI address,
Use the DMA-API to get the MSI address. This address will be written to
our PCI config space and to the register which determines which AXI
address the DWC IP will spoof for incoming MSI irqs.
Since it is a PCIe endpoint device, rather than the CPU, that is supposed
to write to the MSI address,
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