Hi,
On Thu, Jan 28, 2016 at 10:16 AM, Doug Anderson wrote:
> Kever,
>
>
> On Wed, Jan 27, 2016 at 10:41 PM, Kever Yang
> wrote:
>> Hi Doug,
>>
>> We are in HOST mode, we only need to receive data from USB camera
>> with RX FIFO, and no need to use TX FIFO for USB webcam, right? :)
>>
>> Any
Kever,
On Wed, Jan 27, 2016 at 10:41 PM, Kever Yang wrote:
> Hi Doug,
>
> We are in HOST mode, we only need to receive data from USB camera
> with RX FIFO, and no need to use TX FIFO for USB webcam, right? :)
>
> Any way, I think we need to NAK this patch after look into the design
> of dwc2
Hi,
On Thu, Jan 28, 2016 at 10:16 AM, Doug Anderson wrote:
> Kever,
>
>
> On Wed, Jan 27, 2016 at 10:41 PM, Kever Yang
> wrote:
>> Hi Doug,
>>
>> We are in HOST mode, we only need to receive data from USB camera
>> with RX FIFO, and no need to
Kever,
On Wed, Jan 27, 2016 at 10:41 PM, Kever Yang wrote:
> Hi Doug,
>
> We are in HOST mode, we only need to receive data from USB camera
> with RX FIFO, and no need to use TX FIFO for USB webcam, right? :)
>
> Any way, I think we need to NAK this patch after look
Hi Doug,
We are in HOST mode, we only need to receive data from USB camera
with RX FIFO, and no need to use TX FIFO for USB webcam, right? :)
Any way, I think we need to NAK this patch after look into the design
of dwc2 controller. Because all the dwc2 controller inside the Rockchip
chips don't
Kever,
On Wed, Jan 27, 2016 at 7:10 PM, Kever Yang wrote:
> Hi Doug,
>
> We are using the minimum FIFO size mode for TX now, which only
> equal to one max packet size.
>
> The addition FIFO size may help shorten the inter-packet data
> prepare latency when the bus/DRAM is busy.
>
> For the
Hi Doug,
We are using the minimum FIFO size mode for TX now, which only
equal to one max packet size.
The addition FIFO size may help shorten the inter-packet data
prepare latency when the bus/DRAM is busy.
For the actual usage in TX, we have very little change to use the
period TX FIFO with
Hi Doug,
We are in HOST mode, we only need to receive data from USB camera
with RX FIFO, and no need to use TX FIFO for USB webcam, right? :)
Any way, I think we need to NAK this patch after look into the design
of dwc2 controller. Because all the dwc2 controller inside the Rockchip
chips don't
Hi Doug,
We are using the minimum FIFO size mode for TX now, which only
equal to one max packet size.
The addition FIFO size may help shorten the inter-packet data
prepare latency when the bus/DRAM is busy.
For the actual usage in TX, we have very little change to use the
period TX FIFO with
Kever,
On Wed, Jan 27, 2016 at 7:10 PM, Kever Yang wrote:
> Hi Doug,
>
> We are using the minimum FIFO size mode for TX now, which only
> equal to one max packet size.
>
> The addition FIFO size may help shorten the inter-packet data
> prepare latency when the bus/DRAM
Looking at rk3288, there are two dwc2 ports. One has 960
total_fifo_size and the other 972.
We're currently assigning 528 + 128 + 256 = 912. That means we're
wasting 48 words on one port and 60 words on the other. Since we have
one settings block for both ports, let's just eat the 48 words
Looking at rk3288, there are two dwc2 ports. One has 960
total_fifo_size and the other 972.
We're currently assigning 528 + 128 + 256 = 912. That means we're
wasting 48 words on one port and 60 words on the other. Since we have
one settings block for both ports, let's just eat the 48 words
12 matches
Mail list logo