Re: [PATCH v5 07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control

On Wed, 2020-11-18 at 11:55 +0800, Ikjoon Jang wrote: > On Mon, Nov 09, 2020 at 10:03:32AM +0800, Weiyi Lu wrote: > > In fact, the en_mask is a combination of divider enable mask > > and pll enable bit(bit0). > > Before this patch, we enabled both divider mask and bit0 in prepare(), > > but only

Re: [PATCH v5 07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control

On Mon, Nov 09, 2020 at 10:03:32AM +0800, Weiyi Lu wrote: > In fact, the en_mask is a combination of divider enable mask > and pll enable bit(bit0). > Before this patch, we enabled both divider mask and bit0 in prepare(), > but only cleared the bit0 in unprepare(). > In the future, we hope en_mask

[PATCH v5 07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control

In fact, the en_mask is a combination of divider enable mask and pll enable bit(bit0). Before this patch, we enabled both divider mask and bit0 in prepare(), but only cleared the bit0 in unprepare(). In the future, we hope en_mask will only be used as divider enable mask. The enable register(CON0)