On 01/11/2018 03:45 PM, Rob Herring wrote:
On Sun, Jan 07, 2018 at 08:17:16PM -0600, David Lechner wrote:
This adds a new binding for the gate clocks present in the CFGCHIP syscon
registers in TI DA8XX SoCs. There are actually other gate clocks in this
block that could be added in the future,
On 01/11/2018 03:45 PM, Rob Herring wrote:
On Sun, Jan 07, 2018 at 08:17:16PM -0600, David Lechner wrote:
This adds a new binding for the gate clocks present in the CFGCHIP syscon
registers in TI DA8XX SoCs. There are actually other gate clocks in this
block that could be added in the future,
On Sun, Jan 07, 2018 at 08:17:16PM -0600, David Lechner wrote:
> This adds a new binding for the gate clocks present in the CFGCHIP syscon
> registers in TI DA8XX SoCs. There are actually other gate clocks in this
> block that could be added in the future, but TBCLK is currently the only
> one
On Sun, Jan 07, 2018 at 08:17:16PM -0600, David Lechner wrote:
> This adds a new binding for the gate clocks present in the CFGCHIP syscon
> registers in TI DA8XX SoCs. There are actually other gate clocks in this
> block that could be added in the future, but TBCLK is currently the only
> one
This adds a new binding for the gate clocks present in the CFGCHIP syscon
registers in TI DA8XX SoCs. There are actually other gate clocks in this
block that could be added in the future, but TBCLK is currently the only
one being used.
Signed-off-by: David Lechner
---
This adds a new binding for the gate clocks present in the CFGCHIP syscon
registers in TI DA8XX SoCs. There are actually other gate clocks in this
block that could be added in the future, but TBCLK is currently the only
one being used.
Signed-off-by: David Lechner
---
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