Re: [PATCH v5 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On Thu, May 17, 2018 at 4:42 PM, John Garry wrote: > On 16/05/2018 05:55, Ganapatrao Kulkarni wrote: >> >> This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory >> Controller(DMC) and Level 3 Cache(L3C). >> > > Hi, > > Just some coding comments below: > >> ThunderX2 has 8 independen

Re: [PATCH v5 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

On 16/05/2018 05:55, Ganapatrao Kulkarni wrote: This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). Hi, Just some coding comments below: ThunderX2 has 8 independent DMC PMUs to capture performance events corresponding to 8 channels of

[PATCH v5 2/2] ThunderX2: Add Cavium ThunderX2 SoC UNCORE PMU driver

This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory Controller(DMC) and Level 3 Cache(L3C). ThunderX2 has 8 independent DMC PMUs to capture performance events corresponding to 8 channels of DDR4 Memory Controller and 16 independent L3C PMUs to capture events corresponding to 16 ti