On Mon, Aug 25, 2014 at 07:59:01PM +0800, Shawn Guo wrote:
> On Wed, May 28, 2014 at 06:50:13PM +0800, Liu Ying wrote:
> > The i.MX PWM version2 is embedded in several i.MX SoCs,
> > such as i.MX27, i.MX51 and i.MX6SL. There is a 4-word(16bit)
> > sample FIFO in this IP. Each FIFO slot
On Wed, May 28, 2014 at 06:50:13PM +0800, Liu Ying wrote:
> The i.MX PWM version2 is embedded in several i.MX SoCs,
> such as i.MX27, i.MX51 and i.MX6SL. There is a 4-word(16bit)
> sample FIFO in this IP. Each FIFO slot determines the duty
> period of a PWM waveform in one full cycle. The IP
On Wed, May 28, 2014 at 06:50:13PM +0800, Liu Ying wrote:
The i.MX PWM version2 is embedded in several i.MX SoCs,
such as i.MX27, i.MX51 and i.MX6SL. There is a 4-word(16bit)
sample FIFO in this IP. Each FIFO slot determines the duty
period of a PWM waveform in one full cycle. The IP spec
On Mon, Aug 25, 2014 at 07:59:01PM +0800, Shawn Guo wrote:
On Wed, May 28, 2014 at 06:50:13PM +0800, Liu Ying wrote:
The i.MX PWM version2 is embedded in several i.MX SoCs,
such as i.MX27, i.MX51 and i.MX6SL. There is a 4-word(16bit)
sample FIFO in this IP. Each FIFO slot determines the
The i.MX PWM version2 is embedded in several i.MX SoCs,
such as i.MX27, i.MX51 and i.MX6SL. There is a 4-word(16bit)
sample FIFO in this IP. Each FIFO slot determines the duty
period of a PWM waveform in one full cycle. The IP spec
mentions that we should not write a fourth sample because
the
The i.MX PWM version2 is embedded in several i.MX SoCs,
such as i.MX27, i.MX51 and i.MX6SL. There is a 4-word(16bit)
sample FIFO in this IP. Each FIFO slot determines the duty
period of a PWM waveform in one full cycle. The IP spec
mentions that we should not write a fourth sample because
the
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