RE: [PATCH v6 12/13] phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)

kernel.org; Lokesh Vutla > > Subject: [PATCH v6 12/13] phy: cadence: phy-cadence-sierra: Model > PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) > > EXTERNAL MAIL > > > Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has > two inputs, plllc_refclk (input fro

[PATCH v6 12/13] phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)

Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon