Re: [PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-02-16 Thread Peter De Schrijver
On Fri, Feb 13, 2015 at 12:39:03PM +0200, Mikko Perttunen wrote: > On 02/12/2015 04:19 PM, Peter De Schrijver wrote: > >On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote: > >>From: Paul Walmsley > >> > >>The DVCO present in the DFLL IP block has a separate reset line, > >>exposed

Re: [PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-02-16 Thread Peter De Schrijver
On Fri, Feb 13, 2015 at 12:39:03PM +0200, Mikko Perttunen wrote: On 02/12/2015 04:19 PM, Peter De Schrijver wrote: On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote: From: Paul Walmsley pwalms...@nvidia.com The DVCO present in the DFLL IP block has a separate reset line,

Re: [PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-02-13 Thread Mikko Perttunen
On 02/12/2015 04:19 PM, Peter De Schrijver wrote: On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote: From: Paul Walmsley The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something

Re: [PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-02-13 Thread Mikko Perttunen
On 02/12/2015 04:19 PM, Peter De Schrijver wrote: On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote: From: Paul Walmsley pwalms...@nvidia.com The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC

Re: [PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-02-12 Thread Peter De Schrijver
On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote: > From: Paul Walmsley > > The DVCO present in the DFLL IP block has a separate reset line, > exposed via the CAR IP block. This reset line is asserted upon SoC > reset. Unless something (such as the DFLL driver) deasserts this >

Re: [PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-02-12 Thread Peter De Schrijver
On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote: From: Paul Walmsley pwalms...@nvidia.com The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver)

[PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-01-08 Thread Mikko Perttunen
From: Paul Walmsley The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and writes to the DFLL IP

[PATCH v7 05/16] clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-01-08 Thread Mikko Perttunen
From: Paul Walmsley pwalms...@nvidia.com The DVCO present in the DFLL IP block has a separate reset line, exposed via the CAR IP block. This reset line is asserted upon SoC reset. Unless something (such as the DFLL driver) deasserts this line, the DVCO will not oscillate, although reads and