On Fri, Feb 13, 2015 at 12:39:03PM +0200, Mikko Perttunen wrote:
> On 02/12/2015 04:19 PM, Peter De Schrijver wrote:
> >On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote:
> >>From: Paul Walmsley
> >>
> >>The DVCO present in the DFLL IP block has a separate reset line,
> >>exposed
On Fri, Feb 13, 2015 at 12:39:03PM +0200, Mikko Perttunen wrote:
On 02/12/2015 04:19 PM, Peter De Schrijver wrote:
On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote:
From: Paul Walmsley pwalms...@nvidia.com
The DVCO present in the DFLL IP block has a separate reset line,
On 02/12/2015 04:19 PM, Peter De Schrijver wrote:
On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote:
From: Paul Walmsley
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something
On 02/12/2015 04:19 PM, Peter De Schrijver wrote:
On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote:
From: Paul Walmsley pwalms...@nvidia.com
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote:
> From: Paul Walmsley
>
> The DVCO present in the DFLL IP block has a separate reset line,
> exposed via the CAR IP block. This reset line is asserted upon SoC
> reset. Unless something (such as the DFLL driver) deasserts this
>
On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote:
From: Paul Walmsley pwalms...@nvidia.com
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver)
From: Paul Walmsley
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and writes to the
DFLL IP
From: Paul Walmsley pwalms...@nvidia.com
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset. Unless something (such as the DFLL driver) deasserts this
line, the DVCO will not oscillate, although reads and
8 matches
Mail list logo