On Wed, Mar 27, 2019 at 11:52 PM Greg KH wrote:
>
> On Wed, Mar 27, 2019 at 12:01:50PM -0700, Patrick Venture wrote:
> > On Wed, Mar 27, 2019 at 11:54 AM Greg KH wrote:
> > >
> > > On Wed, Mar 27, 2019 at 11:44:36AM -0700, Patrick Venture wrote:
> > > > On Wed, Mar 27, 2019 at 11:28 AM Greg KH
On Wed, Mar 27, 2019 at 12:01:50PM -0700, Patrick Venture wrote:
> On Wed, Mar 27, 2019 at 11:54 AM Greg KH wrote:
> >
> > On Wed, Mar 27, 2019 at 11:44:36AM -0700, Patrick Venture wrote:
> > > On Wed, Mar 27, 2019 at 11:28 AM Greg KH
> > > wrote:
> > > >
> > > > On Tue, Mar 12, 2019 at
On Wed, Mar 27, 2019 at 12:01 PM Patrick Venture wrote:
>
> On Wed, Mar 27, 2019 at 11:54 AM Greg KH wrote:
> >
> > On Wed, Mar 27, 2019 at 11:44:36AM -0700, Patrick Venture wrote:
> > > On Wed, Mar 27, 2019 at 11:28 AM Greg KH
> > > wrote:
> > > >
> > > > On Tue, Mar 12, 2019 at 09:31:01AM
On Wed, Mar 27, 2019 at 11:54 AM Greg KH wrote:
>
> On Wed, Mar 27, 2019 at 11:44:36AM -0700, Patrick Venture wrote:
> > On Wed, Mar 27, 2019 at 11:28 AM Greg KH wrote:
> > >
> > > On Tue, Mar 12, 2019 at 09:31:01AM -0700, Patrick Venture wrote:
> > > > + phys_addr_t mem_base;
> > >
> > > Is
On Wed, Mar 27, 2019 at 11:44:36AM -0700, Patrick Venture wrote:
> On Wed, Mar 27, 2019 at 11:28 AM Greg KH wrote:
> >
> > On Tue, Mar 12, 2019 at 09:31:01AM -0700, Patrick Venture wrote:
> > > + phys_addr_t mem_base;
> >
> > Is this really a 32bit value?
>
> It's going to be a 32-bit value
On Wed, Mar 27, 2019 at 11:28 AM Greg KH wrote:
>
> On Tue, Mar 12, 2019 at 09:31:01AM -0700, Patrick Venture wrote:
> > + phys_addr_t mem_base;
>
> Is this really a 32bit value?
It's going to be a 32-bit value if this is in the dts for one of the
correspondingly supported aspeed models.
>
On Tue, Mar 12, 2019 at 09:31:01AM -0700, Patrick Venture wrote:
> + phys_addr_t mem_base;
Is this really a 32bit value?
Your ioctl thinks it is:
> +struct aspeed_p2a_ctrl_mapping {
> + __u32 addr;
Does this driver not work on a 64bit kernel?
> + __u32 length;
> + __u32 flags;
The ASPEED AST2400, and AST2500 in some configurations include a
PCI-to-AHB MMIO bridge. This bridge allows a server to read and write
in the BMC's physical address space. This feature is especially useful
when using this bridge to send large files to the BMC.
The host may use this to send down
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