On Fri, Mar 27, 2015 at 10:18:39AM +0100, Sascha Hauer wrote:
> This patchset contains the initial common clock support for Mediatek SoCs.
> Mediatek SoC's clock architecture comprises of various PLLs, dividers, muxes
> and clock gates.
Can be pulled here:
The following changes since commit
This patchset contains the initial common clock support for Mediatek SoCs.
Mediatek SoC's clock architecture comprises of various PLLs, dividers, muxes
and clock gates.
Changes in v9:
- rename 'lock' to 'mt81xx_clk_lock' to get better lockdep output
Changes in v8:
- add patch to allow to put
This patchset contains the initial common clock support for Mediatek SoCs.
Mediatek SoC's clock architecture comprises of various PLLs, dividers, muxes
and clock gates.
Changes in v9:
- rename 'lock' to 'mt81xx_clk_lock' to get better lockdep output
Changes in v8:
- add patch to allow to put
On Fri, Mar 27, 2015 at 10:18:39AM +0100, Sascha Hauer wrote:
This patchset contains the initial common clock support for Mediatek SoCs.
Mediatek SoC's clock architecture comprises of various PLLs, dividers, muxes
and clock gates.
Can be pulled here:
The following changes since commit
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