> Subject: Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
> On Wed, 25 Nov 2015 05:40:49 +
> Bharat Kumar Gogada wrote:
>
> > > On Thu, 19 Nov 2015 11:05:23 +0530
> > > Bharat Kumar Gogada wrote:
> >
On Wed, 25 Nov 2015 14:23:29 +0530
Amit Tomer wrote:
> Sorry to intervene but just trying to learn from your comments.
>
> > You have plenty, and that's the whole of your device space. *All of it*. So
> > just take the base address of your PCIe controller, and be done with
> > it.
>
> but
Sorry to intervene but just trying to learn from your comments.
> You have plenty, and that's the whole of your device space. *All of it*. So
> just take the base address of your PCIe controller, and be done with
> it.
but isn't few of PCIe controller's registers itself are mapped
here(base
On Wed, 25 Nov 2015 05:40:49 +
Bharat Kumar Gogada wrote:
> > On Thu, 19 Nov 2015 11:05:23 +0530
> > Bharat Kumar Gogada wrote:
> >
> > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> > >
> > > Signed-off-by: Bharat Kumar Gogada
> > > Signed-off-by: Ravi Kiran Gummaluri
>
> On Thu, 19 Nov 2015 11:05:23 +0530
> Bharat Kumar Gogada wrote:
>
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada
> > Signed-off-by: Ravi Kiran Gummaluri
> > Acked-by: Rob Herring
> > ---
> > +
> > +#define MSI_ADDRESS
On Thu, 19 Nov 2015 11:05:23 +0530
Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
>
> Signed-off-by: Bharat Kumar Gogada
> Signed-off-by: Ravi Kiran Gummaluri
> Acked-by: Rob Herring
> ---
> Changes for v9:
> - Modified logic in nwl_irq_domain_alloc t
Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
Signed-off-by: Bharat Kumar Gogada
Signed-off-by: Ravi Kiran Gummaluri
Acked-by: Rob Herring
---
Changes for v9:
- Modified logic in nwl_irq_domain_alloc to check availabilty of contiguous
hw irq for multi MSI.
- Removed allocation of
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