On Tue, Jul 26, 2016 at 09:11:49AM -0500, Timur Tabi wrote:
> Will Deacon wrote:
> >The kernel really needs to support both of those platforms :/
> >
> >For the memory-mapped counter registers, the architecture says:
> >
> > `If the implementation supports 64-bit atomic accesses, then the
> >
On Tue, Jul 26, 2016 at 09:11:49AM -0500, Timur Tabi wrote:
> Will Deacon wrote:
> >The kernel really needs to support both of those platforms :/
> >
> >For the memory-mapped counter registers, the architecture says:
> >
> > `If the implementation supports 64-bit atomic accesses, then the
> >
Hi all,
On 27 July 2016 at 11:33, Jisheng Zhang wrote:
> +1
>
> On Tue, 26 Jul 2016 09:11:49 -0500 Timur Tabi wrote:
>
>> Will Deacon wrote:
>> > The kernel really needs to support both of those platforms :/
>> >
>> > For the memory-mapped counter registers, the
Hi all,
On 27 July 2016 at 11:33, Jisheng Zhang wrote:
> +1
>
> On Tue, 26 Jul 2016 09:11:49 -0500 Timur Tabi wrote:
>
>> Will Deacon wrote:
>> > The kernel really needs to support both of those platforms :/
>> >
>> > For the memory-mapped counter registers, the architecture says:
>> >
>> >
+1
On Tue, 26 Jul 2016 09:11:49 -0500 Timur Tabi wrote:
> Will Deacon wrote:
> > The kernel really needs to support both of those platforms :/
> >
> > For the memory-mapped counter registers, the architecture says:
> >
> >`If the implementation supports 64-bit atomic accesses, then the
> >
+1
On Tue, 26 Jul 2016 09:11:49 -0500 Timur Tabi wrote:
> Will Deacon wrote:
> > The kernel really needs to support both of those platforms :/
> >
> > For the memory-mapped counter registers, the architecture says:
> >
> >`If the implementation supports 64-bit atomic accesses, then the
> >
Will Deacon wrote:
The kernel really needs to support both of those platforms :/
For the memory-mapped counter registers, the architecture says:
`If the implementation supports 64-bit atomic accesses, then the
CNTV_CVAL register must be accessible as an atomic 64-bit value.'
which is
Will Deacon wrote:
The kernel really needs to support both of those platforms :/
For the memory-mapped counter registers, the architecture says:
`If the implementation supports 64-bit atomic accesses, then the
CNTV_CVAL register must be accessible as an atomic 64-bit value.'
which is
Hi Russell King,
On 26 July 2016 at 06:49, Russell King - ARM Linux
wrote:
> On Mon, Jul 25, 2016 at 05:31:45PM +0100, Will Deacon wrote:
>> On Mon, Jul 25, 2016 at 11:55:49PM +0800, Fu Wei wrote:
>> > On 25 July 2016 at 23:31, Will Deacon wrote:
>> >
Hi Russell King,
On 26 July 2016 at 06:49, Russell King - ARM Linux
wrote:
> On Mon, Jul 25, 2016 at 05:31:45PM +0100, Will Deacon wrote:
>> On Mon, Jul 25, 2016 at 11:55:49PM +0800, Fu Wei wrote:
>> > On 25 July 2016 at 23:31, Will Deacon wrote:
>> > > On Mon, Jul 25, 2016 at 11:27:02PM +0800,
On Mon, Jul 25, 2016 at 05:31:45PM +0100, Will Deacon wrote:
> On Mon, Jul 25, 2016 at 11:55:49PM +0800, Fu Wei wrote:
> > On 25 July 2016 at 23:31, Will Deacon wrote:
> > > On Mon, Jul 25, 2016 at 11:27:02PM +0800, fu@linaro.org wrote:
> > >> From: Fu Wei
On Mon, Jul 25, 2016 at 05:31:45PM +0100, Will Deacon wrote:
> On Mon, Jul 25, 2016 at 11:55:49PM +0800, Fu Wei wrote:
> > On 25 July 2016 at 23:31, Will Deacon wrote:
> > > On Mon, Jul 25, 2016 at 11:27:02PM +0800, fu@linaro.org wrote:
> > >> From: Fu Wei
> > >>
> > >> This patch simplify
On Mon, Jul 25, 2016 at 11:55:49PM +0800, Fu Wei wrote:
> On 25 July 2016 at 23:31, Will Deacon wrote:
> > On Mon, Jul 25, 2016 at 11:27:02PM +0800, fu@linaro.org wrote:
> >> From: Fu Wei
> >>
> >> This patch simplify arch_counter_get_cntvct_mem
On Mon, Jul 25, 2016 at 11:55:49PM +0800, Fu Wei wrote:
> On 25 July 2016 at 23:31, Will Deacon wrote:
> > On Mon, Jul 25, 2016 at 11:27:02PM +0800, fu@linaro.org wrote:
> >> From: Fu Wei
> >>
> >> This patch simplify arch_counter_get_cntvct_mem function by
> >> using readq to get 64-bit
Will Deacon wrote:
> {
>- u32 vct_lo, vct_hi, tmp_hi;
>-
>- do {
>- vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
>- vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
>- tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
>- } while (vct_hi
Will Deacon wrote:
> {
>- u32 vct_lo, vct_hi, tmp_hi;
>-
>- do {
>- vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
>- vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
>- tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
>- } while (vct_hi
Hi Will,
On 25 July 2016 at 23:31, Will Deacon wrote:
> On Mon, Jul 25, 2016 at 11:27:02PM +0800, fu@linaro.org wrote:
>> From: Fu Wei
>>
>> This patch simplify arch_counter_get_cntvct_mem function by
>> using readq to get 64-bit CNTVCT value instead
Hi Will,
On 25 July 2016 at 23:31, Will Deacon wrote:
> On Mon, Jul 25, 2016 at 11:27:02PM +0800, fu@linaro.org wrote:
>> From: Fu Wei
>>
>> This patch simplify arch_counter_get_cntvct_mem function by
>> using readq to get 64-bit CNTVCT value instead of readl_relaxed.
>>
>> Signed-off-by:
On Mon, Jul 25, 2016 at 11:27:02PM +0800, fu@linaro.org wrote:
> From: Fu Wei
>
> This patch simplify arch_counter_get_cntvct_mem function by
> using readq to get 64-bit CNTVCT value instead of readl_relaxed.
>
> Signed-off-by: Fu Wei
> ---
>
On Mon, Jul 25, 2016 at 11:27:02PM +0800, fu@linaro.org wrote:
> From: Fu Wei
>
> This patch simplify arch_counter_get_cntvct_mem function by
> using readq to get 64-bit CNTVCT value instead of readl_relaxed.
>
> Signed-off-by: Fu Wei
> ---
> drivers/clocksource/arm_arch_timer.c | 10
From: Fu Wei
This patch simplify arch_counter_get_cntvct_mem function by
using readq to get 64-bit CNTVCT value instead of readl_relaxed.
Signed-off-by: Fu Wei
---
drivers/clocksource/arm_arch_timer.c | 10 +-
1 file changed, 1 insertion(+), 9
From: Fu Wei
This patch simplify arch_counter_get_cntvct_mem function by
using readq to get 64-bit CNTVCT value instead of readl_relaxed.
Signed-off-by: Fu Wei
---
drivers/clocksource/arm_arch_timer.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git
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