Re: [PATCHv1 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.

I apologize upfront for the double post, but I discovered and issue with the v1 version I sent. On Fri, May 22, 2015 at 11:03 AM, Moritz Fischer wrote: > The Xilinx LogiCORE IP mailbox is a FPGA core that allows for > interprocessor communication via AXI4 memory mapped / AXI4 stream >

[PATCHv1 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.

The Xilinx LogiCORE IP mailbox is a FPGA core that allows for interprocessor communication via AXI4 memory mapped / AXI4 stream interfaces. It is single channel per core and allows for transmit and receive. Signed-off-by: Moritz Fischer --- MAINTAINERS | 7 +

Re: [PATCHv1 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.

I apologize upfront for the double post, but I discovered and issue with the v1 version I sent. On Fri, May 22, 2015 at 11:03 AM, Moritz Fischer moritz.fisc...@ettus.com wrote: The Xilinx LogiCORE IP mailbox is a FPGA core that allows for interprocessor communication via AXI4 memory mapped /

[PATCHv1 2/2] mailbox: Adding driver for Xilinx LogiCORE IP mailbox.

The Xilinx LogiCORE IP mailbox is a FPGA core that allows for interprocessor communication via AXI4 memory mapped / AXI4 stream interfaces. It is single channel per core and allows for transmit and receive. Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com --- MAINTAINERS