Re: [PATCHv2] clk: socfpga: allow for multiple parents on Arria10 periph clocks

On 02/22, dingu...@opensource.altera.com wrote: > From: Dinh Nguyen > > There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can > have multiple parents. Fix up the __socfpga_periph_init() to call > of_clk_parent_fill() that will return the appropriate number of parents. > > A

[PATCHv2] clk: socfpga: allow for multiple parents on Arria10 periph clocks

From: Dinh Nguyen There are some Arria10 clocks of type "altr,socfpga-a10-perip-clk" that can have multiple parents. Fix up the __socfpga_periph_init() to call of_clk_parent_fill() that will return the appropriate number of parents. Also, update __socfpga_gate_init() to call of_clk_parent_fill()