* Sebastian Andrzej Siewior [180504 17:50]:
> On 2018-05-04 10:39:31 [-0700], Tony Lindgren wrote:
> > Uhh sorry I managed to commit also a patch I was testing while
> > updating patch comments.. Will send out v3 shortly, this can be
> > ignored.
>
> I assumed you were
* Sebastian Andrzej Siewior [180504 17:50]:
> On 2018-05-04 10:39:31 [-0700], Tony Lindgren wrote:
> > Uhh sorry I managed to commit also a patch I was testing while
> > updating patch comments.. Will send out v3 shortly, this can be
> > ignored.
>
> I assumed you were helping out to sneak a
On 2018-05-04 10:39:31 [-0700], Tony Lindgren wrote:
> Uhh sorry I managed to commit also a patch I was testing while
> updating patch comments.. Will send out v3 shortly, this can be
> ignored.
I assumed you were helping out to sneak a patch in.
> Regards,
>
> Tony
Sebastian
On 2018-05-04 10:39:31 [-0700], Tony Lindgren wrote:
> Uhh sorry I managed to commit also a patch I was testing while
> updating patch comments.. Will send out v3 shortly, this can be
> ignored.
I assumed you were helping out to sneak a patch in.
> Regards,
>
> Tony
Sebastian
* Tony Lindgren [180504 17:33]:
> I noticed that unused UARTs won't necessarily idle properly always
> unless at least one byte tx transfer is done first.
> ---
> arch/arm/mach-actions/platsmp.c | 6 +++---
> arch/arm/mach-exynos/platsmp.c | 12 ++--
>
* Tony Lindgren [180504 17:33]:
> I noticed that unused UARTs won't necessarily idle properly always
> unless at least one byte tx transfer is done first.
> ---
> arch/arm/mach-actions/platsmp.c | 6 +++---
> arch/arm/mach-exynos/platsmp.c | 12 ++--
>
I noticed that unused UARTs won't necessarily idle properly always
unless at least one byte tx transfer is done first.
After some debugging I narrowed down the problem to the scr register
dma configuration bits that need to be set before softreset for the
clocks to idle. Unless we do this, the
I noticed that unused UARTs won't necessarily idle properly always
unless at least one byte tx transfer is done first.
After some debugging I narrowed down the problem to the scr register
dma configuration bits that need to be set before softreset for the
clocks to idle. Unless we do this, the
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