Re: [PATCHv2 07/11] EDAC, altera: Add status offset & masks

Hi Boris, On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer In preparation for the Arria10 peripheral ECCs, the IRQ status needs to be determined because the IRQs are shared. The IRQ status register is read to determine if the IRQ

Re: [PATCHv2 07/11] EDAC, altera: Add status offset & masks

Hi Boris, On 03/07/2016 01:43 PM, ttha...@opensource.altera.com wrote: From: Thor Thayer In preparation for the Arria10 peripheral ECCs, the IRQ status needs to be determined because the IRQs are shared. The IRQ status register is read to determine if the IRQ was for this ECC peripheral.

[PATCHv2 07/11] EDAC, altera: Add status offset & masks

From: Thor Thayer In preparation for the Arria10 peripheral ECCs, the IRQ status needs to be determined because the IRQs are shared. The IRQ status register is read to determine if the IRQ was for this ECC peripheral. Cyclone5 and Arria5 have dedicated IRQs so the

[PATCHv2 07/11] EDAC, altera: Add status offset & masks

From: Thor Thayer In preparation for the Arria10 peripheral ECCs, the IRQ status needs to be determined because the IRQs are shared. The IRQ status register is read to determine if the IRQ was for this ECC peripheral. Cyclone5 and Arria5 have dedicated IRQs so the confirmation mechanism is not