Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-24 Thread Thor Thayer
On Wed, 2014-04-23 at 16:54 +0200, Borislav Petkov wrote: > On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote: > > From: Thor Thayer > > > > Added EDAC support for reporting ECC errors of CycloneV > > and ArriaV SDRAM controller. > > - The SDRAM Controller registers are used by

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-24 Thread Thor Thayer
On Wed, 2014-04-23 at 16:54 +0200, Borislav Petkov wrote: On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers are

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-23 Thread Borislav Petkov
On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote: > From: Thor Thayer > > Added EDAC support for reporting ECC errors of CycloneV > and ArriaV SDRAM controller. > - The SDRAM Controller registers are used by the FPGA bridge so > these are accessed through the syscon

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-23 Thread Borislav Petkov
On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers are used by the FPGA bridge so these are accessed through the

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-21 Thread Thor Thayer
On Mon, 2014-04-21 at 12:27 +0200, Pavel Machek wrote: > Hi! > > > From: Thor Thayer > > > > Added EDAC support for reporting ECC errors of CycloneV > > and ArriaV SDRAM controller. > > - The SDRAM Controller registers are used by the FPGA bridge so > > these are accessed through the syscon

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-21 Thread Pavel Machek
Hi! > From: Thor Thayer > > Added EDAC support for reporting ECC errors of CycloneV > and ArriaV SDRAM controller. > - The SDRAM Controller registers are used by the FPGA bridge so > these are accessed through the syscon interface. > - The configuration of the SDRAM memory size for the EDAC

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-21 Thread Pavel Machek
Hi! From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers are used by the FPGA bridge so these are accessed through the syscon interface. - The configuration of the SDRAM memory size for

Re: [PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-21 Thread Thor Thayer
On Mon, 2014-04-21 at 12:27 +0200, Pavel Machek wrote: Hi! From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers are used by the FPGA bridge so these are accessed through the

[PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-15 Thread tthayer
From: Thor Thayer Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers are used by the FPGA bridge so these are accessed through the syscon interface. - The configuration of the SDRAM memory size for the EDAC framework is

[PATCHv2 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV

2014-04-15 Thread tthayer
From: Thor Thayer ttha...@altera.com Added EDAC support for reporting ECC errors of CycloneV and ArriaV SDRAM controller. - The SDRAM Controller registers are used by the FPGA bridge so these are accessed through the syscon interface. - The configuration of the SDRAM memory size for the EDAC