On Wed, 2014-04-23 at 16:54 +0200, Borislav Petkov wrote:
> On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote:
> > From: Thor Thayer
> >
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SDRAM Controller registers are used by
On Wed, 2014-04-23 at 16:54 +0200, Borislav Petkov wrote:
On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are
On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote:
> From: Thor Thayer
>
> Added EDAC support for reporting ECC errors of CycloneV
> and ArriaV SDRAM controller.
> - The SDRAM Controller registers are used by the FPGA bridge so
> these are accessed through the syscon
On Tue, Apr 15, 2014 at 06:30:10PM -0500, ttha...@altera.com wrote:
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the
On Mon, 2014-04-21 at 12:27 +0200, Pavel Machek wrote:
> Hi!
>
> > From: Thor Thayer
> >
> > Added EDAC support for reporting ECC errors of CycloneV
> > and ArriaV SDRAM controller.
> > - The SDRAM Controller registers are used by the FPGA bridge so
> > these are accessed through the syscon
Hi!
> From: Thor Thayer
>
> Added EDAC support for reporting ECC errors of CycloneV
> and ArriaV SDRAM controller.
> - The SDRAM Controller registers are used by the FPGA bridge so
> these are accessed through the syscon interface.
> - The configuration of the SDRAM memory size for the EDAC
Hi!
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for
On Mon, 2014-04-21 at 12:27 +0200, Pavel Machek wrote:
Hi!
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the
From: Thor Thayer
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC framework
is
From: Thor Thayer ttha...@altera.com
Added EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controller.
- The SDRAM Controller registers are used by the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC
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