Re: [PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi Sören On Mon, May 5, 2014 at 6:16 PM, Sören Brinkmann wrote: > > Hi Thor, > > On Mon, 2014-05-05 at 05:52PM -0500, ttha...@altera.com wrote: > > From: Thor Thayer > > > > Addition of the Altera SDRAM controller bindings and device > > tree changes to the Altera SoC project. The "syscon"

Re: [PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi Sören On Mon, May 5, 2014 at 6:16 PM, Sören Brinkmann soren.brinkm...@xilinx.com wrote: Hi Thor, On Mon, 2014-05-05 at 05:52PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes to the

Re: [PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi Thor, On Mon, 2014-05-05 at 05:52PM -0500, ttha...@altera.com wrote: > From: Thor Thayer > > Addition of the Altera SDRAM controller bindings and device > tree changes to the Altera SoC project. The "syscon" parameter > is included here because the SDRAM EDAC bits are shared with the SDRAM >

[PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

From: Thor Thayer Addition of the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. The "syscon" parameter is included here because the SDRAM EDAC bits are shared with the SDRAM configuration bits. --- v2: Changes to SoC SDRAM EDAC code. V3: Implement code

[PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. The syscon parameter is included here because the SDRAM EDAC bits are shared with the SDRAM configuration bits. --- v2: Changes to SoC SDRAM EDAC code. V3:

Re: [PATCHv3 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller

Hi Thor, On Mon, 2014-05-05 at 05:52PM -0500, ttha...@altera.com wrote: From: Thor Thayer ttha...@altera.com Addition of the Altera SDRAM controller bindings and device tree changes to the Altera SoC project. The syscon parameter is included here because the SDRAM EDAC bits are shared with