On Fri, Nov 07, 2014 at 10:31:20AM -0600, Dinh Nguyen wrote:
> If it's okay, can you please pick up this series, once everything is
> cleaned up? I just checked to make sure that there aren't any merge
> conflicts in the DTS files in this series against DTS patches that I
> have queue up for 3.19,
Hi Boris,
On 11/06/2014 10:31 AM, Borislav Petkov wrote:
> Hi Thor,
>
> On Tue, Nov 04, 2014 at 04:57:44PM -0600, Thor Thayer wrote:
>> We want to at least separate L2/OCRAM ECC from the SDRAM ECC because
>> 1) the SDRAM preparation can take almost 2 seconds on boot and some
>> customers need a
Hi Boris,
On 11/06/2014 10:31 AM, Borislav Petkov wrote:
Hi Thor,
On Tue, Nov 04, 2014 at 04:57:44PM -0600, Thor Thayer wrote:
We want to at least separate L2/OCRAM ECC from the SDRAM ECC because
1) the SDRAM preparation can take almost 2 seconds on boot and some
customers need a faster
On Fri, Nov 07, 2014 at 10:31:20AM -0600, Dinh Nguyen wrote:
If it's okay, can you please pick up this series, once everything is
cleaned up? I just checked to make sure that there aren't any merge
conflicts in the DTS files in this series against DTS patches that I
have queue up for 3.19, and
Hi Thor,
On Tue, Nov 04, 2014 at 04:57:44PM -0600, Thor Thayer wrote:
> We want to at least separate L2/OCRAM ECC from the SDRAM ECC because
> 1) the SDRAM preparation can take almost 2 seconds on boot and some
> customers need a faster boot time.
> 2) the SDRAM has an ECC initialization
Hi Thor,
On Tue, Nov 04, 2014 at 04:57:44PM -0600, Thor Thayer wrote:
We want to at least separate L2/OCRAM ECC from the SDRAM ECC because
1) the SDRAM preparation can take almost 2 seconds on boot and some
customers need a faster boot time.
2) the SDRAM has an ECC initialization dependency
Hi Boris!
On 11/04/2014 09:12 AM, Borislav Petkov wrote:
On Thu, Oct 30, 2014 at 10:32:10AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory
On Thu, Oct 30, 2014 at 10:32:10AM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer
>
> Adding L2 Cache and On-Chip RAM EDAC support for the
> Altera SoCs using the EDAC device model. The SDRAM
> controller is using the Memory Controller model. All
> Altera EDAC functions live in
On Thu, Oct 30, 2014 at 10:32:10AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model. All
Altera
Hi Boris!
On 11/04/2014 09:12 AM, Borislav Petkov wrote:
On Thu, Oct 30, 2014 at 10:32:10AM -0500, ttha...@opensource.altera.com wrote:
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model. All
Altera EDAC functions live in altera_edac.c.
Signed-off-by: Thor Thayer
---
v2: Fix L2 dependency comments.
v3: Move
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model. All
Altera EDAC functions live in altera_edac.c.
Signed-off-by: Thor Thayer
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