On Mon, May 12, 2014 at 7:12 PM, Borislav Petkov wrote:
> On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote:
>> + ptemp[0] = 0x5A5A5A5A;
>> + ptemp[1] = 0xA5A5A5A5;
>> + /* Clear the error injection bits */
>> + regmap_write(drvdata->mc_vbase, CTLCFG, read_reg);
On Mon, May 12, 2014 at 7:12 PM, Borislav Petkov b...@alien8.de wrote:
On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote:
+ ptemp[0] = 0x5A5A5A5A;
+ ptemp[1] = 0xA5A5A5A5;
+ /* Clear the error injection bits */
+ regmap_write(drvdata-mc_vbase, CTLCFG,
On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote:
> + ptemp[0] = 0x5A5A5A5A;
> + ptemp[1] = 0xA5A5A5A5;
> + /* Clear the error injection bits */
> + regmap_write(drvdata->mc_vbase, CTLCFG, read_reg);
> + /* Ensure it has been written out */
> + wmb();
> +
From: Thor Thayer
This patch adds EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controllers.
- The SDRAM Controller registers are shared with the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory size for the EDAC
From: Thor Thayer ttha...@altera.com
This patch adds EDAC support for reporting ECC errors of CycloneV
and ArriaV SDRAM controllers.
- The SDRAM Controller registers are shared with the FPGA bridge so
these are accessed through the syscon interface.
- The configuration of the SDRAM memory
On Mon, May 12, 2014 at 06:36:57PM -0500, ttha...@altera.com wrote:
+ ptemp[0] = 0x5A5A5A5A;
+ ptemp[1] = 0xA5A5A5A5;
+ /* Clear the error injection bits */
+ regmap_write(drvdata-mc_vbase, CTLCFG, read_reg);
+ /* Ensure it has been written out */
+ wmb();
+
+
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