On 12/02/2014 09:25 AM, Mark Rutland wrote:
Hi,
+/* MPU L2 Register Defines */
+#define ALTR_MPUL2_CONTROL_OFFSET 0x100
+#define ALTR_MPUL2_CTL_CACHE_EN_MASKBIT(0)
These are just standard PL310 register definitions, no?
Yes.
[...]
+static void *ocram_alloc_mem(size_t size,
Hi,
> +/* MPU L2 Register Defines */
> +#define ALTR_MPUL2_CONTROL_OFFSET 0x100
> +#define ALTR_MPUL2_CTL_CACHE_EN_MASKBIT(0)
These are just standard PL310 register definitions, no?
[...]
> +static void *ocram_alloc_mem(size_t size, void **other)
> +{
> + struct device_node
Hi,
+/* MPU L2 Register Defines */
+#define ALTR_MPUL2_CONTROL_OFFSET 0x100
+#define ALTR_MPUL2_CTL_CACHE_EN_MASKBIT(0)
These are just standard PL310 register definitions, no?
[...]
+static void *ocram_alloc_mem(size_t size, void **other)
+{
+ struct device_node *np;
+
On 12/02/2014 09:25 AM, Mark Rutland wrote:
Hi,
+/* MPU L2 Register Defines */
+#define ALTR_MPUL2_CONTROL_OFFSET 0x100
+#define ALTR_MPUL2_CTL_CACHE_EN_MASKBIT(0)
These are just standard PL310 register definitions, no?
Yes.
[...]
+static void *ocram_alloc_mem(size_t size,
From: Thor Thayer
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation can take almost 2 seconds on boot and some
From: Thor Thayer ttha...@opensource.altera.com
Adding L2 Cache and On-Chip RAM EDAC support for the
Altera SoCs using the EDAC device model. The SDRAM
controller is using the Memory Controller model.
The SDRAM ECC is a separate Kconfig option because:
1) the SDRAM preparation can take almost 2
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