Re: [PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

2015-02-07 Thread Russell King - ARM Linux
On Thu, Jan 08, 2015 at 08:53:55PM -0600, ttha...@opensource.altera.com wrote: > +static int altr_edac_device_probe(struct platform_device *pdev) > +{ > + struct edac_device_ctl_info *dci; > + struct altr_edac_device_dev *drvdata; > + struct resource *r; > + int res = 0; > +

Re: [PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

2015-02-07 Thread Russell King - ARM Linux
On Thu, Jan 08, 2015 at 08:53:55PM -0600, ttha...@opensource.altera.com wrote: +static int altr_edac_device_probe(struct platform_device *pdev) +{ + struct edac_device_ctl_info *dci; + struct altr_edac_device_dev *drvdata; + struct resource *r; + int res = 0; + struct

Re: [PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

2015-02-06 Thread Thor Thayer
On 02/06/2015 01:17 PM, Mark Rutland wrote: On Fri, Jan 09, 2015 at 02:53:55AM +, ttha...@opensource.altera.com wrote: From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller

Re: [PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

2015-02-06 Thread Mark Rutland
On Fri, Jan 09, 2015 at 02:53:55AM +, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Adding L2 Cache and On-Chip RAM EDAC support for the > Altera SoCs using the EDAC device model. The SDRAM > controller is using the Memory Controller model. > > Each type of ECC is

Re: [PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

2015-02-06 Thread Mark Rutland
On Fri, Jan 09, 2015 at 02:53:55AM +, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each

Re: [PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

2015-02-06 Thread Thor Thayer
On 02/06/2015 01:17 PM, Mark Rutland wrote: On Fri, Jan 09, 2015 at 02:53:55AM +, ttha...@opensource.altera.com wrote: From: Thor Thayer ttha...@opensource.altera.com Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is

[PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

2015-01-08 Thread tthayer
From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. The SDRAM ECC is a separate Kconfig option because: 1) the SDRAM

[PATCHv6 4/5] edac: altera: Add Altera L2 Cache and OCRAM EDAC Support

2015-01-08 Thread tthayer
From: Thor Thayer ttha...@opensource.altera.com Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. The SDRAM ECC is a separate Kconfig option