Re: [PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-02-08 Thread Borislav Petkov
On Mon, Feb 08, 2016 at 10:10:53AM -0600, Thor Thayer wrote: > Understood. I did get a conditional ACK from Rob Herring on the DT portion > of the patch from the last revision (as long as I made the changes he > suggested which I did in this patch). There may be other comments though. Ah, and I

Re: [PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-02-08 Thread Thor Thayer
Hi Boris. On 02/08/2016 05:39 AM, Borislav Petkov wrote: On Wed, Jan 27, 2016 at 10:13:20AM -0600, ttha...@opensource.altera.com wrote: From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory

Re: [PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-02-08 Thread Borislav Petkov
On Wed, Jan 27, 2016 at 10:13:20AM -0600, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Adding L2 Cache and On-Chip RAM EDAC support for the > Altera SoCs using the EDAC device model. The SDRAM > controller is using the Memory Controller model. > > Each type of ECC is

Re: [PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-02-08 Thread Thor Thayer
Hi Boris. On 02/08/2016 05:39 AM, Borislav Petkov wrote: On Wed, Jan 27, 2016 at 10:13:20AM -0600, ttha...@opensource.altera.com wrote: From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM

Re: [PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-02-08 Thread Borislav Petkov
On Mon, Feb 08, 2016 at 10:10:53AM -0600, Thor Thayer wrote: > Understood. I did get a conditional ACK from Rob Herring on the DT portion > of the patch from the last revision (as long as I made the changes he > suggested which I did in this patch). There may be other comments though. Ah, and I

Re: [PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-02-08 Thread Borislav Petkov
On Wed, Jan 27, 2016 at 10:13:20AM -0600, ttha...@opensource.altera.com wrote: > From: Thor Thayer > > Adding L2 Cache and On-Chip RAM EDAC support for the > Altera SoCs using the EDAC device model. The SDRAM > controller is using the Memory Controller model. > >

[PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-27 Thread tthayer
From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer --- v9: Improve device tree node release. Free

[PATCHv9 1/4] EDAC, altera: Add Altera L2 Cache and OCRAM EDAC Support

2016-01-27 Thread tthayer
From: Thor Thayer Adding L2 Cache and On-Chip RAM EDAC support for the Altera SoCs using the EDAC device model. The SDRAM controller is using the Memory Controller model. Each type of ECC is individually configurable. Signed-off-by: Thor Thayer