Hi Stephane,
On Mon, 29 Oct 2012 16:15:46 +0100, Stephane Eranian wrote:
> + /*
> + * use the mapping table for bit 0-15
> + */
> + val = pebs_data_source[dse.ld_dse];
I guess you meant bit 0-3, right?
Thanks,
Namhyung
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Hi Stephane,
On Mon, 29 Oct 2012 16:15:46 +0100, Stephane Eranian wrote:
+ /*
+ * use the mapping table for bit 0-15
+ */
+ val = pebs_data_source[dse.ld_dse];
I guess you meant bit 0-3, right?
Thanks,
Namhyung
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> I agree. I did that because it was the easiest thing I could think of.
> Discovered I had to deal with all of this just two days ago when I
> rebased. Wasn't too happy to have to deal with this at the last minute.
I'll repost, as soon as I debugged why Jiri's version of my 31/33 parser patch
On Mon, Oct 29, 2012 at 10:16 PM, Andi Kleen wrote:
>> > Why do you need to replace the whole table?
>> >
>> Because I am extending them with one or two events based on cpu
>> model. That was the easiest way of doing this instead of playing
>> some kind of malloc+copy trick.
>
> I did malloc and
> > Why do you need to replace the whole table?
> >
> Because I am extending them with one or two events based on cpu
> model. That was the easiest way of doing this instead of playing
> some kind of malloc+copy trick.
I did malloc and copy.
>
> > BTW I still think my approach in the v4 Haswell
On Mon, 2012-10-29 at 21:39 +0100, Stephane Eranian wrote:
> But I think the right mechanism would be one where you
> can add events at boot time based on CPU model. It could be used
> to add the common events as well in the common part of the init
> code.
mlin once posted something like that,
On Mon, Oct 29, 2012 at 8:42 PM, Andi Kleen wrote:
>> +
>> +struct attribute *nhm_events_attrs[] = {
>> + EVENT_PTR(CPU_CYCLES),
>> + EVENT_PTR(INSTRUCTIONS),
>> + EVENT_PTR(CACHE_REFERENCES),
>> + EVENT_PTR(CACHE_MISSES),
>> + EVENT_PTR(BRANCH_INSTRUCTIONS),
>> +
> +
> +struct attribute *nhm_events_attrs[] = {
> + EVENT_PTR(CPU_CYCLES),
> + EVENT_PTR(INSTRUCTIONS),
> + EVENT_PTR(CACHE_REFERENCES),
> + EVENT_PTR(CACHE_MISSES),
> + EVENT_PTR(BRANCH_INSTRUCTIONS),
> + EVENT_PTR(BRANCH_MISSES),
> + EVENT_PTR(BUS_CYCLES),
> +
On Mon, 2012-10-29 at 16:43 +0100, Stephane Eranian wrote:
> You meant fll, instead I think.
Oh, yes, too small font I guess.
> Well, that would work too, but I am trying to factorize the code
> with Precise Store which is a later patch.
Yeah, just found that, its fine the way it is. Just
On Mon, Oct 29, 2012 at 4:38 PM, Peter Zijlstra wrote:
> On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
>> + fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
>> +
>> perf_sample_data_init(, 0, event->hw.last_period);
>>
>> + data.period = event->hw.last_period;
On Mon, Oct 29, 2012 at 4:35 PM, Peter Zijlstra wrote:
> On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
>> +static u64 load_latency_data(u64 status)
>> +{
>> + union intel_x86_pebs_dse dse;
>> + u64 val;
>> + int model = boot_cpu_data.x86_model;
>> + int fam =
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
> + fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
> +
> perf_sample_data_init(, 0, event->hw.last_period);
>
> + data.period = event->hw.last_period;
> + sample_type = event->attr.sample_type;
> +
> +
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
> +static u64 load_latency_data(u64 status)
> +{
> + union intel_x86_pebs_dse dse;
> + u64 val;
> + int model = boot_cpu_data.x86_model;
> + int fam = boot_cpu_data.x86;
> +
> + dse.val = status;
> +
> +
On Mon, Oct 29, 2012 at 4:23 PM, Peter Zijlstra wrote:
> On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
>> +EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x100b,umask=0x1,ldlat=3");
>> +EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
>
> I haven't fully grokked
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
> +EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x100b,umask=0x1,ldlat=3");
> +EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
I haven't fully grokked the macro magic yet, but event=0x100b seems
wrong, event only
This patch adds support for memory profiling using the
PEBS Load Latency facility.
Load accesses are sampled by HW and the instruction
address, data address, load latency, data source, tlb,
locked information can be saved in the sampling buffer
if using the PERF_SAMPLE_COST (for latency),
On Mon, 2012-10-29 at 21:39 +0100, Stephane Eranian wrote:
But I think the right mechanism would be one where you
can add events at boot time based on CPU model. It could be used
to add the common events as well in the common part of the init
code.
mlin once posted something like that, it
Why do you need to replace the whole table?
Because I am extending them with one or two events based on cpu
model. That was the easiest way of doing this instead of playing
some kind of malloc+copy trick.
I did malloc and copy.
BTW I still think my approach in the v4 Haswell patchkit
On Mon, Oct 29, 2012 at 10:16 PM, Andi Kleen a...@linux.intel.com wrote:
Why do you need to replace the whole table?
Because I am extending them with one or two events based on cpu
model. That was the easiest way of doing this instead of playing
some kind of malloc+copy trick.
I did
I agree. I did that because it was the easiest thing I could think of.
Discovered I had to deal with all of this just two days ago when I
rebased. Wasn't too happy to have to deal with this at the last minute.
I'll repost, as soon as I debugged why Jiri's version of my 31/33 parser patch
This patch adds support for memory profiling using the
PEBS Load Latency facility.
Load accesses are sampled by HW and the instruction
address, data address, load latency, data source, tlb,
locked information can be saved in the sampling buffer
if using the PERF_SAMPLE_COST (for latency),
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
+EVENT_ATTR_STR(mem-loads, mem_ld_nhm, event=0x100b,umask=0x1,ldlat=3);
+EVENT_ATTR_STR(mem-loads, mem_ld_snb, event=0xcd,umask=0x1,ldlat=3);
I haven't fully grokked the macro magic yet, but event=0x100b seems
wrong, event only takes 8
On Mon, Oct 29, 2012 at 4:23 PM, Peter Zijlstra pet...@infradead.org wrote:
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
+EVENT_ATTR_STR(mem-loads, mem_ld_nhm, event=0x100b,umask=0x1,ldlat=3);
+EVENT_ATTR_STR(mem-loads, mem_ld_snb, event=0xcd,umask=0x1,ldlat=3);
I haven't fully
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
+static u64 load_latency_data(u64 status)
+{
+ union intel_x86_pebs_dse dse;
+ u64 val;
+ int model = boot_cpu_data.x86_model;
+ int fam = boot_cpu_data.x86;
+
+ dse.val = status;
+
+ /*
+
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
+ fll = event-hw.flags PERF_X86_EVENT_PEBS_LDLAT;
+
perf_sample_data_init(data, 0, event-hw.last_period);
+ data.period = event-hw.last_period;
+ sample_type = event-attr.sample_type;
+
+ /*
+
On Mon, Oct 29, 2012 at 4:35 PM, Peter Zijlstra pet...@infradead.org wrote:
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
+static u64 load_latency_data(u64 status)
+{
+ union intel_x86_pebs_dse dse;
+ u64 val;
+ int model = boot_cpu_data.x86_model;
+ int
On Mon, Oct 29, 2012 at 4:38 PM, Peter Zijlstra pet...@infradead.org wrote:
On Mon, 2012-10-29 at 16:15 +0100, Stephane Eranian wrote:
+ fll = event-hw.flags PERF_X86_EVENT_PEBS_LDLAT;
+
perf_sample_data_init(data, 0, event-hw.last_period);
+ data.period =
On Mon, 2012-10-29 at 16:43 +0100, Stephane Eranian wrote:
You meant fll, instead I think.
Oh, yes, too small font I guess.
Well, that would work too, but I am trying to factorize the code
with Precise Store which is a later patch.
Yeah, just found that, its fine the way it is. Just looked
+
+struct attribute *nhm_events_attrs[] = {
+ EVENT_PTR(CPU_CYCLES),
+ EVENT_PTR(INSTRUCTIONS),
+ EVENT_PTR(CACHE_REFERENCES),
+ EVENT_PTR(CACHE_MISSES),
+ EVENT_PTR(BRANCH_INSTRUCTIONS),
+ EVENT_PTR(BRANCH_MISSES),
+ EVENT_PTR(BUS_CYCLES),
+
On Mon, Oct 29, 2012 at 8:42 PM, Andi Kleen a...@linux.intel.com wrote:
+
+struct attribute *nhm_events_attrs[] = {
+ EVENT_PTR(CPU_CYCLES),
+ EVENT_PTR(INSTRUCTIONS),
+ EVENT_PTR(CACHE_REFERENCES),
+ EVENT_PTR(CACHE_MISSES),
+ EVENT_PTR(BRANCH_INSTRUCTIONS),
+
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