On Tue, 6 Oct 2020 15:23:46 +0200, Bert Vermeulen wrote:
> If a flash chip has more than 16MB capacity but its BFPT reports
> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
>
> The check in spi_nor_set_addr_width() doesn't catch it because addr_width
> did get set. This
On 07/10/20 12:59PM, Vignesh Raghavendra wrote:
>
>
> On 10/6/20 8:48 PM, Pratyush Yadav wrote:
> > On 06/10/20 03:23PM, Bert Vermeulen wrote:
> >> If a flash chip has more than 16MB capacity but its BFPT reports
> >> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
> >>
>
On 10/6/20 8:48 PM, Pratyush Yadav wrote:
> On 06/10/20 03:23PM, Bert Vermeulen wrote:
>> If a flash chip has more than 16MB capacity but its BFPT reports
>> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
>>
>> The check in spi_nor_set_addr_width() doesn't catch it
On Tue, Oct 06, 2020 at 03:23:46PM +0200, Bert Vermeulen wrote:
> If a flash chip has more than 16MB capacity but its BFPT reports
> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
>
> The check in spi_nor_set_addr_width() doesn't catch it because addr_width
> did get set.
On 06/10/20 03:23PM, Bert Vermeulen wrote:
> If a flash chip has more than 16MB capacity but its BFPT reports
> BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
>
> The check in spi_nor_set_addr_width() doesn't catch it because addr_width
> did get set. This fixes that
If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_set_addr_width() doesn't catch it because addr_width
did get set. This fixes that check.
Fixes: f9acd7fa80be ("mtd: spi-nor: sfdp: default
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