[RESEND PATCH v2 2/2] drivers: clk: zynqmp: Update fraction clock check from custom type flags

From: Tejas Patel Older firmware version sets BIT(13) in clkflag to mark a divider as fractional divider. Updated firmware version sets BIT(4) in type flags to mark a divider as fractional divider since BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk framework flags. To support

[RESEND PATCH v2 2/2] drivers: clk: zynqmp: Update fraction clock check from custom type flags

From: Tejas Patel Older firmware version sets BIT(13) in clkflag to mark a divider as fractional divider. Updated firmware version sets BIT(4) in type flags to mark a divider as fractional divider since BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk framework flags. To support