Hi "Ramuthevar,Vadivel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.10-rc1 next-20201030]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use
Hi Miquel,
Thank you for the review comments...
On 30/10/2020 4:23 pm, Miquel Raynal wrote:
+
+static const struct of_device_id ebu_nand_match[] = {
+ { .compatible = "intel,nand-controller", },
No version or soc in the compatible? (not mandatory).
Yes, you're right, it should be
Hi Miquel,
On 30/10/2020 4:23 pm, Miquel Raynal wrote:
Hello,
+static const struct nand_controller_ops ebu_nand_controller_ops = {
+ .attach_chip = ebu_nand_attach_chip,
+ .setup_interface = ebu_nand_set_timings,
+ .exec_op = ebu_nand_exec_op,
+};
+
+static void
Hello,
> >> +static const struct nand_controller_ops ebu_nand_controller_ops = {
> >> + .attach_chip = ebu_nand_attach_chip,
> >> + .setup_interface = ebu_nand_set_timings,
> >> + .exec_op = ebu_nand_exec_op,
> >> +};
> >> +
> >> +static void ebu_dma_cleanup(struct ebu_nand_controller
Hi Miquel,
Thank you very much for the review comments...
On 28/10/2020 6:20 pm, Miquel Raynal wrote:
Hello,
"Ramuthevar,Vadivel MuruganX"
wrote on Mon, 26 Oct 2020
15:30:21 +0800:
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on
Hello,
"Ramuthevar,Vadivel MuruganX"
wrote on Mon, 26 Oct 2020
15:30:21 +0800:
> From: Ramuthevar Vadivel Murugan
>
> This patch adds the new IP of Nand Flash Controller(NFC) support
> on Intel's Lightning Mountain(LGM) SoC.
>
> DMA is used for burst data transfer operation, also DMA HW
From: Ramuthevar Vadivel Murugan
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8
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