* Peter Ujfalusi | 2014-09-20 00:29:01 [+0300]:
>mask 800 means URXEVT0 (UART0 rx), 400 is UTXEVT0 (UART0 tx) events.
>But it is clear that my theory was not even close to what's going on.
>Do you have some tool which can be used to reproduce this issue?
The latest uart patch set is at
* Peter Ujfalusi | 2014-09-20 00:29:01 [+0300]:
mask 800 means URXEVT0 (UART0 rx), 400 is UTXEVT0 (UART0 tx) events.
But it is clear that my theory was not even close to what's going on.
Do you have some tool which can be used to reproduce this issue?
The latest uart patch set is at
On 09/18/2014 07:12 PM, Sebastian Andrzej Siewior wrote:
> * Peter Ujfalusi | 2014-09-18 12:42:24 [+0300]:
>
>> My hunch on what could be causing this that we might have unhandled dma event
>> and another comes. This will flag the EDMA_EMR register. Any change in this
>> register will assert
On 09/18/2014 07:12 PM, Sebastian Andrzej Siewior wrote:
* Peter Ujfalusi | 2014-09-18 12:42:24 [+0300]:
My hunch on what could be causing this that we might have unhandled dma event
and another comes. This will flag the EDMA_EMR register. Any change in this
register will assert error
* Peter Ujfalusi | 2014-09-18 12:42:24 [+0300]:
>My hunch on what could be causing this that we might have unhandled dma event
>and another comes. This will flag the EDMA_EMR register. Any change in this
>register will assert error interrupt which can only be cleared by writing to
>EDMA_EMRC
On 09/10/2014 10:39 PM, Sebastian Andrzej Siewior wrote:
> With 8250-dma, 8250-omap and am335x I observe the following:
>
> - start a RX transfer which will finish once the FIFO has enough data
> - The TX side starts a large TX transfer, say 1244 bytes. It takes approx
> 102ms for the transfer
On 09/10/2014 10:39 PM, Sebastian Andrzej Siewior wrote:
With 8250-dma, 8250-omap and am335x I observe the following:
- start a RX transfer which will finish once the FIFO has enough data
- The TX side starts a large TX transfer, say 1244 bytes. It takes approx
102ms for the transfer to
* Peter Ujfalusi | 2014-09-18 12:42:24 [+0300]:
My hunch on what could be causing this that we might have unhandled dma event
and another comes. This will flag the EDMA_EMR register. Any change in this
register will assert error interrupt which can only be cleared by writing to
EDMA_EMRC
With 8250-dma, 8250-omap and am335x I observe the following:
- start a RX transfer which will finish once the FIFO has enough data
- The TX side starts a large TX transfer, say 1244 bytes. It takes approx
102ms for the transfer to complete
- cancel the RX transfer & start the RX transfer a few
With 8250-dma, 8250-omap and am335x I observe the following:
- start a RX transfer which will finish once the FIFO has enough data
- The TX side starts a large TX transfer, say 1244 bytes. It takes approx
102ms for the transfer to complete
- cancel the RX transfer start the RX transfer a few
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