On 10/06/2019 15:12, Abel Vesa wrote:
> On 19-06-10 14:51:48, Marc Zyngier wrote:
>> On 10/06/2019 14:38, Abel Vesa wrote:
>>> On 19-06-10 14:24:11, Marc Zyngier wrote:
Abel,
On 10/06/2019 13:13, Abel Vesa wrote:
> i.MX8MQ is missing the wake_request signals from GIC to GPCv2. Th
On 19-06-10 14:51:48, Marc Zyngier wrote:
> On 10/06/2019 14:38, Abel Vesa wrote:
> > On 19-06-10 14:24:11, Marc Zyngier wrote:
> >> Abel,
> >>
> >> On 10/06/2019 13:13, Abel Vesa wrote:
> >>> i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This
> >>> indirectly
> >>> breaks cpuidle
On 10/06/2019 14:38, Abel Vesa wrote:
> On 19-06-10 14:24:11, Marc Zyngier wrote:
>> Abel,
>>
>> On 10/06/2019 13:13, Abel Vesa wrote:
>>> i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This
>>> indirectly
>>> breaks cpuidle support due to inability to wake target cores on IPIs.
>>
On 19-06-10 14:24:11, Marc Zyngier wrote:
> Abel,
>
> On 10/06/2019 13:13, Abel Vesa wrote:
> > i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This
> > indirectly
> > breaks cpuidle support due to inability to wake target cores on IPIs.
> >
> > Here is the link to the errata (see
Abel,
On 10/06/2019 13:13, Abel Vesa wrote:
> i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly
> breaks cpuidle support due to inability to wake target cores on IPIs.
>
> Here is the link to the errata (see e11171):
>
> https://www.nxp.com/docs/en/errata/IMX8MDQLQ_0
On 6/10/2019 3:15 PM, Abel Vesa wrote:
> i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly
> breaks cpuidle support due to inability to wake target cores on IPIs.
>
> Now, in order to fix this, we can trigger IRQ 32 (hwirq 0) to all the cores by
> setting 12th bit in I
i.MX8MQ is missing the wake_request signals from GIC to GPCv2. This indirectly
breaks cpuidle support due to inability to wake target cores on IPIs.
Here is the link to the errata (see e11171):
https://www.nxp.com/docs/en/errata/IMX8MDQLQ_0N14W.pdf
Now, in order to fix this, we can trigger IRQ 3
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