This divisor is controlled by the firmware, we don't want the clock subsystem to update it inadvertently.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulie...@suse.de> --- drivers/clk/bcm/clk-bcm2835.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index c2772dfb155a..5aea110672f3 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -465,6 +465,7 @@ struct bcm2835_pll_divider_data { u32 hold_mask; u32 fixed_divider; u32 flags; + u32 div_flags; }; struct bcm2835_clock_data { @@ -1349,7 +1350,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, divider->div.reg = cprman->regs + data->a2w_reg; divider->div.shift = A2W_PLL_DIV_SHIFT; divider->div.width = A2W_PLL_DIV_BITS; - divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; + divider->div.flags = data->div_flags | CLK_DIVIDER_MAX_AT_ZERO; divider->div.lock = &cprman->regs_lock; divider->div.hw.init = &init; divider->div.table = NULL; @@ -1676,7 +1677,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .load_mask = CM_PLLB_LOADARM, .hold_mask = CM_PLLB_HOLDARM, .fixed_divider = 1, - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE), + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, + .div_flags = CLK_DIVIDER_READ_ONLY), /* * PLLC is the core PLL, used to drive the core VPU clock. -- 2.21.0