On 10/31/2012 04:32 AM, Mike Turquette wrote:
> Quoting Stephen Warren (2012-10-30 11:02:05)
>> On 10/29/2012 12:32 PM, Mike Turquette wrote:
>>> Quoting Stephen Warren (2012-10-23 14:45:56)
What do people think of this? Does it sound like a good idea to go ahead
with a reset subsystem?
On 10/31/2012 04:32 AM, Mike Turquette wrote:
Quoting Stephen Warren (2012-10-30 11:02:05)
On 10/29/2012 12:32 PM, Mike Turquette wrote:
Quoting Stephen Warren (2012-10-23 14:45:56)
What do people think of this? Does it sound like a good idea to go ahead
with a reset subsystem? Should we
On 10/29/2012 12:32 PM, Mike Turquette wrote:
> Quoting Stephen Warren (2012-10-23 14:45:56)
>> What do people think of this? Does it sound like a good idea to go ahead
>> with a reset subsystem? Should we simply add a new API to the common clock
>> subsystem instead (and assume that reset and
On 10/29/2012 12:32 PM, Mike Turquette wrote:
Quoting Stephen Warren (2012-10-23 14:45:56)
What do people think of this? Does it sound like a good idea to go ahead
with a reset subsystem? Should we simply add a new API to the common clock
subsystem instead (and assume that reset and clock
Quoting Stephen Warren (2012-10-23 14:45:56)
> What do people think of this? Does it sound like a good idea to go ahead
> with a reset subsystem? Should we simply add a new API to the common clock
> subsystem instead (and assume that reset and clock domains match 1:1).
> Should this be implemented
Quoting Stephen Warren (2012-10-23 14:45:56)
What do people think of this? Does it sound like a good idea to go ahead
with a reset subsystem? Should we simply add a new API to the common clock
subsystem instead (and assume that reset and clock domains match 1:1).
Should this be implemented as
From: Stephen Warren
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA, ...) designs.
Such a binding would allow the creation of a "reset subsystem", which
could replace APIs such as the following Tegra-specific API:
void
From: Stephen Warren swar...@nvidia.com
This binding is intended to represent the hardware reset signals present
internally in most IC (SoC, FPGA, ...) designs.
Such a binding would allow the creation of a reset subsystem, which
could replace APIs such as the following Tegra-specific API:
void
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