Re: [RFC PATCH] irqchip/gic-v3: Correct the usage of GICD_CTLR's RWP field

Hi Andre, On 2019/5/13 16:37, Andre Przywara wrote: On Mon, 13 May 2019 04:15:54 + Zenghui Yu wrote: Hi, As per ARM IHI 0069D, GICD_CTLR's RWP field tracks updates to: GICD_CTLR's Group Enable bits, for transitions from 1 to 0 only GICD_CTLR's ARE bits, E1NWF bit and DS

Re: [RFC PATCH] irqchip/gic-v3: Correct the usage of GICD_CTLR's RWP field

On Mon, 13 May 2019 04:15:54 + Zenghui Yu wrote: Hi, > As per ARM IHI 0069D, GICD_CTLR's RWP field tracks updates to: > > GICD_CTLR's Group Enable bits, for transitions from 1 to 0 only > GICD_CTLR's ARE bits, E1NWF bit and DS bit (if we have) > GICD_ICENABLER > > We

[RFC PATCH] irqchip/gic-v3: Correct the usage of GICD_CTLR's RWP field

As per ARM IHI 0069D, GICD_CTLR's RWP field tracks updates to: GICD_CTLR's Group Enable bits, for transitions from 1 to 0 only GICD_CTLR's ARE bits, E1NWF bit and DS bit (if we have) GICD_ICENABLER We seemed use this field in an inappropriate way, somewhere in the GIC-v3