Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Peter Zijlstra writes: > On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote: >> I also wrote a small C utility[1], with a bit of code borrowed from the >> kernel, for reading the TSC on all CPUs. It starts a high priority >> thread per CPU, tries to synchronize them and prints out

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Peter Zijlstra writes: > On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote: >> I also wrote a small C utility[1], with a bit of code borrowed from the >> kernel, for reading the TSC on all CPUs. It starts a high priority >> thread per CPU, tries to synchronize them and prints out

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Dave Hansen writes: > On 11/09/2015 02:02 PM, Peter Zijlstra wrote: >> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: >>> The Intel Xeon E5 processor family suffers from errata[1] BT81: >> >>> +#ifdef CONFIG_X86_TSC >>> + /* >>> +* Xeon E5 BT81 errata: TSC is not

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Peter Zijlstra writes: > On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote: >> I also wrote a small C utility[1], with a bit of code borrowed from the >> kernel, for reading the TSC on all CPUs. It starts a high priority >> thread per CPU, tries to synchronize them and prints out

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Peter Zijlstra writes: > On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote: >> I also wrote a small C utility[1], with a bit of code borrowed from the >> kernel, for reading the TSC on all CPUs. It starts a high priority >> thread per CPU, tries to synchronize them and prints out

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Dave Hansen writes: > On 11/09/2015 02:02 PM, Peter Zijlstra wrote: >> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: >>> The Intel Xeon E5 processor family suffers from errata[1] BT81: >> >>> +#ifdef CONFIG_X86_TSC >>> + /* >>> +* Xeon E5 BT81 errata: TSC is not

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On 11/09/2015 02:02 PM, Peter Zijlstra wrote: > On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: >> The Intel Xeon E5 processor family suffers from errata[1] BT81: > >> +#ifdef CONFIG_X86_TSC >> +/* >> + * Xeon E5 BT81 errata: TSC is not affected by warm reset. >> +

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote: > I also wrote a small C utility[1], with a bit of code borrowed from the > kernel, for reading the TSC on all CPUs. It starts a high priority > thread per CPU, tries to synchronize them and prints out the TSC values > and their

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On Wed, Nov 11, 2015 at 09:41:25AM -0600, Gratian Crisan wrote: > I also wrote a small C utility[1], with a bit of code borrowed from the > kernel, for reading the TSC on all CPUs. It starts a high priority > thread per CPU, tries to synchronize them and prints out the TSC values > and their

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On 11/09/2015 02:02 PM, Peter Zijlstra wrote: > On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: >> The Intel Xeon E5 processor family suffers from errata[1] BT81: > >> +#ifdef CONFIG_X86_TSC >> +/* >> + * Xeon E5 BT81 errata: TSC is not affected by warm reset. >> +

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Josh Hunt writes: > On Tue, Nov 10, 2015 at 1:47 PM, Gratian Crisan wrote: >> >> The observed behavior does seem to match BT81 errata i.e. the TSC does >> not get reset on warm reboots and it is otherwise stable. >> > If you have a simple testcase to reproduce the problem I'd be > interested in

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Josh Hunt writes: > On Tue, Nov 10, 2015 at 1:47 PM, Gratian Crisan wrote: >> >> The observed behavior does seem to match BT81 errata i.e. the TSC does >> not get reset on warm reboots and it is otherwise stable. >> > If you have a simple testcase to reproduce the problem

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On Tue, Nov 10, 2015 at 1:47 PM, Gratian Crisan wrote: > > The observed behavior does seem to match BT81 errata i.e. the TSC does > not get reset on warm reboots and it is otherwise stable. > If you have a simple testcase to reproduce the problem I'd be interested in seeing it. -- Josh -- To

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Josh Hunt writes: > On Tue, Nov 10, 2015 at 12:24 PM, Josh Hunt wrote: >> >> On Mon, Nov 9, 2015 at 4:02 PM, Peter Zijlstra wrote: >>> >>> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: >>> >>> > The Intel Xeon E5 processor family suffers from errata[1] BT81: >>> >>> >

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On Tue, Nov 10, 2015 at 12:24 PM, Josh Hunt wrote: > > On Mon, Nov 9, 2015 at 4:02 PM, Peter Zijlstra wrote: >> >> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: >> >> > The Intel Xeon E5 processor family suffers from errata[1] BT81: >> >> > +#ifdef CONFIG_X86_TSC >> > +

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On Tue, Nov 10, 2015 at 12:24 PM, Josh Hunt wrote: > > On Mon, Nov 9, 2015 at 4:02 PM, Peter Zijlstra wrote: >> >> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: >> >> > The Intel Xeon E5 processor family suffers from errata[1]

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

Josh Hunt writes: > On Tue, Nov 10, 2015 at 12:24 PM, Josh Hunt wrote: >> >> On Mon, Nov 9, 2015 at 4:02 PM, Peter Zijlstra wrote: >>> >>> On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: >>> >>> > The Intel Xeon E5 processor

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On Tue, Nov 10, 2015 at 1:47 PM, Gratian Crisan wrote: > > The observed behavior does seem to match BT81 errata i.e. the TSC does > not get reset on warm reboots and it is otherwise stable. > If you have a simple testcase to reproduce the problem I'd be interested in seeing

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: > The Intel Xeon E5 processor family suffers from errata[1] BT81: > +#ifdef CONFIG_X86_TSC > + /* > + * Xeon E5 BT81 errata: TSC is not affected by warm reset. > + * The TSC registers for CPUs other than CPU0

[RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

From: Gratian Crisan The Intel Xeon E5 processor family suffers from errata[1] BT81: "TSC is Not Affected by Warm Reset. Problem: The TSC (Time Stamp Counter MSR 10H) should be cleared on reset. Due to this erratum the TSC is not affected by warm reset. Implication: The TSC is not cleared by a

Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: > The Intel Xeon E5 processor family suffers from errata[1] BT81: > +#ifdef CONFIG_X86_TSC > + /* > + * Xeon E5 BT81 errata: TSC is not affected by warm reset. > + * The TSC registers for CPUs other than CPU0

[RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs with offset error

From: Gratian Crisan The Intel Xeon E5 processor family suffers from errata[1] BT81: "TSC is Not Affected by Warm Reset. Problem: The TSC (Time Stamp Counter MSR 10H) should be cleared on reset. Due to this erratum the TSC is not affected by warm reset. Implication: The