On 12/03/21 11:23AM, tudor.amba...@microchip.com wrote:
> On 3/12/21 12:10 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > On 12/03/21 09:09AM, tudor.amba...@microchip.com wrote:
> >> On 3/11/21 9:12 PM,
On 12/03/21 02:32PM, Michael Walle wrote:
> Am 2021-03-11 20:12, schrieb Pratyush Yadav:
> > The main problem here is telling the controller where to find the
> > pattern and how to read it. This RFC uses nvmem cells which point to a
> > fixed partition containing the data to do the reads. It
On 3/12/21 3:32 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Am 2021-03-11 20:12, schrieb Pratyush Yadav:
>> The main problem here is telling the controller where to find the
>> pattern and how to read it. This RFC
Am 2021-03-11 20:12, schrieb Pratyush Yadav:
The main problem here is telling the controller where to find the
pattern and how to read it. This RFC uses nvmem cells which point to a
fixed partition containing the data to do the reads. It depends on [0]
and [1].
The obvious problem with this is
Am 2021-03-12 12:07, schrieb Pratyush Yadav:
On 12/03/21 11:20AM, Michael Walle wrote:
Am 2021-03-12 11:10, schrieb Pratyush Yadav:
> There is usually a delay from when the flash drives the data line (IOW,
> puts a data bit on it) and when the signal reaches the controller. This
> delay can
On 3/12/21 12:10 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 12/03/21 09:09AM, tudor.amba...@microchip.com wrote:
>> On 3/11/21 9:12 PM, Pratyush Yadav wrote:
>>> EXTERNAL EMAIL: Do not click links or open
On 12/03/21 11:20AM, Michael Walle wrote:
> Am 2021-03-12 11:10, schrieb Pratyush Yadav:
> > There is usually a delay from when the flash drives the data line (IOW,
> > puts a data bit on it) and when the signal reaches the controller. This
> > delay can vary by the flash, board, silicon
Am 2021-03-12 11:10, schrieb Pratyush Yadav:
There is usually a delay from when the flash drives the data line (IOW,
puts a data bit on it) and when the signal reaches the controller. This
delay can vary by the flash, board, silicon characteristics,
temperature, etc.
Temperature might change
On 12/03/21 09:09AM, tudor.amba...@microchip.com wrote:
> On 3/11/21 9:12 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Hi,
> >
> > This series adds support for OSPI PHY calibration on the Cadence OSPI
> >
On 3/11/21 9:12 PM, Pratyush Yadav wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi,
>
> This series adds support for OSPI PHY calibration on the Cadence OSPI
> controller. This calibration procedure is needed to allow high clock
>
Hi,
This series adds support for OSPI PHY calibration on the Cadence OSPI
controller. This calibration procedure is needed to allow high clock
speeds in 8D-8D-8D mode. The procedure reads some pre-determined pattern
data from the flash and runs a sequence of test reads to find out the
optimal
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